diff options
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 162 |
2 files changed, 161 insertions, 6 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 94b5d77..ec44f44 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2020-08-10 Alan Modra <amodra@gmail.com> + * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended + instructions. + +2020-08-10 Alan Modra <amodra@gmail.com> + * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru. Enable icbt for power5, miso for power8. diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 8294c76..d62475e 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -6741,11 +6741,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, 0, {RT}}, {"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, 0, {RT}}, +{"mfudscr", XSPR(31,339, 3), XSPR_MASK, POWER9, 0, {RS}}, {"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN, {RT}}, {"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN, {RT}}, {"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, 0, {RT}}, {"mflr", XSPR(31,339, 8), XSPR_MASK, COM, 0, {RT}}, {"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, 0, {RT}}, +{"mfuamr", XSPR(31,339, 13), XSPR_MASK, POWER9, 0, {RS}}, {"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, 0, {RT}}, {"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, 0, {RT}}, {"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN, {RT}}, @@ -6756,9 +6758,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, 0, {RT}}, {"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, 0, {RT}}, {"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, 0, {RT}}, +{"mfamr", XSPR(31,339, 29), XSPR_MASK, POWER7, 0, {RS}}, +{"mfpidr", XSPR(31,339, 48), XSPR_MASK, POWER10, 0, {RS}}, {"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, 0, {RT}}, {"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, 0, {RT}}, {"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfiamr", XSPR(31,339, 61), XSPR_MASK, POWER10, 0, {RS}}, {"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, 0, {RT}}, {"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, 0, {RT}}, {"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, 0, {RT}}, @@ -6772,16 +6777,28 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, 0, {RT}}, {"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, 0, {RT}}, {"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, 0, {RT}}, +{"mffscr", XSPR(31,339,153), XSPR_MASK, POWER10, 0, {RS}}, {"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, 0, {RT}}, {"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, 0, {RT}}, {"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, 0, {RT}}, {"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, 0, {RT}}, +{"mfuamor", XSPR(31,339,157), XSPR_MASK, POWER7, 0, {RS}}, {"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, 0, {RT}}, {"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, 0, {RT}}, +{"mfpspb", XSPR(31,339,159), XSPR_MASK, POWER10, 0, {RS}}, {"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, 0, {RT}}, +{"mfdpdes", XSPR(31,339,176), XSPR_MASK, POWER10, 0, {RS}}, +{"mfdawr0", XSPR(31,339,180), XSPR_MASK, POWER10, 0, {RS}}, +{"mfdawr1", XSPR(31,339,181), XSPR_MASK, POWER10, 0, {RS}}, +{"mfrpr", XSPR(31,339,186), XSPR_MASK, POWER10, 0, {RS}}, +{"mfciabr", XSPR(31,339,187), XSPR_MASK, POWER10, 0, {RS}}, +{"mfdawrx0", XSPR(31,339,188), XSPR_MASK, POWER10, 0, {RS}}, +{"mfdawrx1", XSPR(31,339,189), XSPR_MASK, POWER10, 0, {RS}}, +{"mfhfscr", XSPR(31,339,190), XSPR_MASK, POWER10, 0, {RS}}, {"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, 0, {RT}}, {"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, 0, {RT}}, {"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, 0, {RT, SPRG}}, +{"mfusprg3", XSPR(31,339,259), XSPR_MASK, POWER10, 0, {RT}}, {"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, {"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, {"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, 0, {RT}}, @@ -6797,20 +6814,37 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN, {RT}}, {"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, 0, {RT}}, {"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, 0, {RT}}, +{"mfhsprg0", XSPR(31,339,304), XSPR_MASK, POWER10, 0, {RS}}, {"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhsprg1", XSPR(31,339,305), XSPR_MASK, POWER10, 0, {RS}}, +{"mfhdisr", XSPR(31,339,306), XSPR_MASK, POWER10, 0, {RS}}, +{"mfhdar", XSPR(31,339,307), XSPR_MASK, POWER10, 0, {RS}}, +{"mfspurr", XSPR(31,339,308), XSPR_MASK, POWER10, 0, {RS}}, {"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfpurr", XSPR(31,339,309), XSPR_MASK, POWER10, 0, {RS}}, {"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhdec", XSPR(31,339,310), XSPR_MASK, POWER10, 0, {RS}}, {"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, 0, {RT}}, {"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhrmor", XSPR(31,339,313), XSPR_MASK, POWER10, 0, {RS}}, {"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhsrr0", XSPR(31,339,314), XSPR_MASK, POWER10, 0, {RS}}, {"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhsrr1", XSPR(31,339,315), XSPR_MASK, POWER10, 0, {RS}}, {"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, 0, {RT}}, {"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, 0, {RT}}, {"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, 0, {RT}}, +{"mflpcr", XSPR(31,339,318), XSPR_MASK, POWER10, 0, {RS}}, {"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, 0, {RT}}, +{"mflpidr", XSPR(31,339,319), XSPR_MASK, POWER10, 0, {RS}}, {"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhmer", XSPR(31,339,336), XSPR_MASK, POWER7, 0, {RS}}, {"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfhmeer", XSPR(31,339,337), XSPR_MASK, POWER7, 0, {RS}}, +{"mfpcr", XSPR(31,339,338), XSPR_MASK, POWER10, 0, {RS}}, +{"mfheir", XSPR(31,339,339), XSPR_MASK, POWER10, 0, {RS}}, {"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, 0, {RT}}, +{"mfamor", XSPR(31,339,349), XSPR_MASK, POWER7, 0, {RS}}, {"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, 0, {RT}}, {"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, 0, {RT}}, {"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, 0, {RT}}, @@ -6827,6 +6861,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, 0, {RT}}, {"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, 0, {RT}}, {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, +{"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, 0, {RS}}, +{"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, 0, {RS}}, +{"mfuspgr0", XSPR(31,339,496), XSPR_MASK, POWER10, 0, {RS}}, +{"mfuspgr1", XSPR(31,339,497), XSPR_MASK, POWER10, 0, {RS}}, +{"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, 0, {RS}}, +{"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, 0, {RS}}, +{"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, 0, {RS}}, +{"mfsmfctrl", XSPR(31,339,511), XSPR_MASK, POWER10, 0, {RS}}, {"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, 0, {RT}}, {"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, 0, {RT}}, {"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, 0, {RT}}, @@ -6851,18 +6893,36 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, 0, {RT}}, {"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, 0, {RT}}, {"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, 0, {RT}}, +{"mfusier2", XSPR(31,339,736), XSPR_MASK, POWER10, 0, {RT}}, +{"mfsier2", XSPR(31,339,736), XSPR_MASK, POWER10, 0, {RT}}, +{"mfusier3", XSPR(31,339,737), XSPR_MASK, POWER10, 0, {RT}}, +{"mfsier3", XSPR(31,339,737), XSPR_MASK, POWER10, 0, {RT}}, +{"mfummcr3", XSPR(31,339,738), XSPR_MASK, POWER10, 0, {RT}}, +{"mfmmcr3", XSPR(31,339,738), XSPR_MASK, POWER10, 0, {RT}}, +{"mfusier", XSPR(31,339,768), XSPR_MASK, POWER10, 0, {RT}}, +{"mfsier", XSPR(31,339,768), XSPR_MASK, POWER10, 0, {RT}}, +{"mfummcra", XSPR(31,339,770), XSPR_MASK, POWER9, 0, {RS}}, +{"mfmmcra", XSPR(31,339,770), XSPR_MASK, POWER7, 0, {RS}}, {"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, -{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER7, 0, {RT}}, {"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, -{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER7, 0, {RT}}, {"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, -{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER7, 0, {RT}}, {"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, -{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER7, 0, {RT}}, {"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, -{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER7, 0, {RT}}, {"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, -{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER9, 0, {RT}}, +{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER7, 0, {RT}}, +{"mfummcr0", XSPR(31,339,779), XSPR_MASK, POWER9, 0, {RS}}, +{"mfmmcr0", XSPR(31,339,779), XSPR_MASK, POWER7, 0, {RS}}, +{"mfusiar", XSPR(31,339,780), XSPR_MASK, POWER9, 0, {RS}}, +{"mfsiar", XSPR(31,339,780), XSPR_MASK, POWER9, 0, {RS}}, +{"mfusdar", XSPR(31,339,781), XSPR_MASK, POWER9, 0, {RS}}, +{"mfsdar", XSPR(31,339,781), XSPR_MASK, POWER9, 0, {RS}}, +{"mfummcr1", XSPR(31,339,782), XSPR_MASK, POWER9, 0, {RS}}, +{"mfmmcr1", XSPR(31,339,782), XSPR_MASK, POWER7, 0, {RS}}, {"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, 0, {RT}}, {"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, 0, {RT}}, {"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, 0, {RT}}, @@ -6876,12 +6936,25 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, 0, {RT}}, {"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, 0, {RT}}, {"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, 0, {RT}}, +{"mfbescrs", XSPR(31,339,800), XSPR_MASK, POWER9, 0, {RS}}, +{"mfbescrsu", XSPR(31,339,801), XSPR_MASK, POWER9, 0, {RS}}, +{"mfbescrr", XSPR(31,339,802), XSPR_MASK, POWER9, 0, {RS}}, +{"mfbescrru", XSPR(31,339,803), XSPR_MASK, POWER9, 0, {RS}}, +{"mfebbhr", XSPR(31,339,804), XSPR_MASK, POWER9, 0, {RS}}, +{"mfebbrr", XSPR(31,339,805), XSPR_MASK, POWER9, 0, {RS}}, +{"mfbescr", XSPR(31,339,806), XSPR_MASK, POWER9, 0, {RS}}, +{"mftar", XSPR(31,339,815), XSPR_MASK, POWER9, 0, {RS}}, +{"mfasdr", XSPR(31,339,816), XSPR_MASK, POWER10, 0, {RS}}, {"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, 0, {RT}}, {"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, 0, {RT}}, {"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, 0, {RT}}, +{"mfpsscr", XSPR(31,339,823), XSPR_MASK, POWER10, 0, {RS}}, {"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, 0, {RT}}, {"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, 0, {RT}}, {"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, 0, {RT}}, +{"mfic", XSPR(31,339,848), XSPR_MASK, POWER8, 0, {RS}}, +{"mfvtb", XSPR(31,339,849), XSPR_MASK, POWER8, 0, {RS}}, +{"mfhpsscr", XSPR(31,339,855), XSPR_MASK, POWER10, 0, {RS}}, {"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, 0, {RT}}, {"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, 0, {RT}}, {"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, 0, {RT}}, @@ -7128,8 +7201,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, 0, {RS}}, {"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, 0, {RS}}, +{"mtudscr", XSPR(31,467, 3), XSPR_MASK, POWER9, 0, {RS}}, {"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, 0, {RS}}, {"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, 0, {RS}}, +{"mtuamr", XSPR(31,467, 13), XSPR_MASK, POWER9, 0, {RS}}, {"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, 0, {RS}}, {"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, 0, {RS}}, {"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN, {RS}}, @@ -7142,13 +7217,20 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, 0, {RS}}, {"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, 0, {RS}}, {"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, 0, {RS}}, +{"mtamr", XSPR(31,467, 29), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpidr", XSPR(31,467, 48), XSPR_MASK, POWER10, 0, {RS}}, {"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, 0, {RS}}, {"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, 0, {RS}}, {"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, 0, {RS}}, {"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, 0, {RS}}, +{"mtiamr", XSPR(31,467, 61), XSPR_MASK, POWER10, 0, {RS}}, {"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, 0, {RS}}, {"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, 0, {RS}}, +{"mttfhar", XSPR(31,467,128), XSPR_MASK, POWER9, 0, {RS}}, +{"mttfiar", XSPR(31,467,129), XSPR_MASK, POWER9, 0, {RS}}, +{"mttexasr", XSPR(31,467,130), XSPR_MASK, POWER9, 0, {RS}}, +{"mttexasru", XSPR(31,467,131), XSPR_MASK, POWER9, 0, {RS}}, {"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, 0, {RS}}, {"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, 0, {RS}}, {"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, 0, {RS}}, @@ -7159,13 +7241,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, 0, {RS}}, {"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, 0, {RS}}, {"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, 0, {RS}}, +{"mtfscr", XSPR(31,467,153), XSPR_MASK, POWER10, 0, {RS}}, {"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, 0, {RS}}, {"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, 0, {RS}}, {"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, 0, {RS}}, {"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, 0, {RS}}, +{"mtuamor", XSPR(31,467,157), XSPR_MASK, POWER7, 0, {RS}}, {"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, 0, {RS}}, {"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, 0, {RS}}, +{"mtpspb", XSPR(31,467,159), XSPR_MASK, POWER10, 0, {RS}}, {"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, 0, {RS}}, +{"mtdpdes", XSPR(31,467,176), XSPR_MASK, POWER10, 0, {RS}}, +{"mtdawr0", XSPR(31,467,180), XSPR_MASK, POWER10, 0, {RS}}, +{"mtdawr1", XSPR(31,467,181), XSPR_MASK, POWER10, 0, {RS}}, +{"mtrpr", XSPR(31,467,186), XSPR_MASK, POWER10, 0, {RS}}, +{"mtciabr", XSPR(31,467,187), XSPR_MASK, POWER10, 0, {RS}}, +{"mtdawrx0", XSPR(31,467,188), XSPR_MASK, POWER10, 0, {RS}}, +{"mtdawrx1", XSPR(31,467,189), XSPR_MASK, POWER10, 0, {RS}}, +{"mthfscr", XSPR(31,467,190), XSPR_MASK, POWER10, 0, {RS}}, {"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, 0, {RS}}, {"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, 0, {RS}}, {"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, 0, {SPRG, RS}}, @@ -7181,20 +7274,38 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN, {RS}}, {"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, 0, {RS}}, {"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, 0, {RS}}, +{"mttbu40", XSPR(31,467,286), XSPR_MASK, POWER10, 0, {RS}}, +{"mthsprg0", XSPR(31,467,304), XSPR_MASK, POWER10, 0, {RS}}, {"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthsprg1", XSPR(31,467,305), XSPR_MASK, POWER10, 0, {RS}}, +{"mthdisr", XSPR(31,467,306), XSPR_MASK, POWER10, 0, {RS}}, +{"mthdar", XSPR(31,467,307), XSPR_MASK, POWER10, 0, {RS}}, +{"mtspurr", XSPR(31,467,308), XSPR_MASK, POWER10, 0, {RS}}, {"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, 0, {RS}}, +{"mtpurr", XSPR(31,467,309), XSPR_MASK, POWER10, 0, {RS}}, {"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthdec", XSPR(31,467,310), XSPR_MASK, POWER10, 0, {RS}}, {"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, 0, {RS}}, {"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthrmor", XSPR(31,467,313), XSPR_MASK, POWER10, 0, {RS}}, {"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthsrr0", XSPR(31,467,314), XSPR_MASK, POWER10, 0, {RS}}, {"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthsrr1", XSPR(31,467,315), XSPR_MASK, POWER10, 0, {RS}}, {"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, 0, {RS}}, {"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, 0, {RS}}, {"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, 0, {RS}}, +{"mtlpcr", XSPR(31,467,318), XSPR_MASK, POWER10, 0, {RS}}, {"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, 0, {RS}}, +{"mtlpidr", XSPR(31,467,319), XSPR_MASK, POWER10, 0, {RS}}, {"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthmer", XSPR(31,467,336), XSPR_MASK, POWER7, 0, {RS}}, {"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, 0, {RS}}, +{"mthmeer", XSPR(31,467,337), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpcr", XSPR(31,467,338), XSPR_MASK, POWER10, 0, {RS}}, +{"mtheir", XSPR(31,467,339), XSPR_MASK, POWER10, 0, {RS}}, {"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, 0, {RS}}, +{"mtamor", XSPR(31,467,349), XSPR_MASK, POWER7, 0, {RS}}, {"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, 0, {RS}}, @@ -7211,6 +7322,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, +{"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, 0, {RS}}, +{"mtuspgr0", XSPR(31,467,496), XSPR_MASK, POWER10, 0, {RS}}, +{"mtuspgr1", XSPR(31,467,497), XSPR_MASK, POWER10, 0, {RS}}, +{"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, 0, {RS}}, +{"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, 0, {RS}}, +{"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, 0, {RS}}, +{"mtsmfctrl", XSPR(31,467,511), XSPR_MASK, POWER10, 0, {RS}}, {"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, 0, {RS}}, {"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, 0, {RS}}, {"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, 0, {RS}}, @@ -7225,12 +7343,44 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, 0, {RS}}, {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, 0, {RS}}, {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, 0, {RS}}, +{"mtsier2", XSPR(31,467,752), XSPR_MASK, POWER10, 0, {RS}}, +{"mtsier3", XSPR(31,467,753), XSPR_MASK, POWER10, 0, {RS}}, +{"mtmmcr3", XSPR(31,467,754), XSPR_MASK, POWER10, 0, {RS}}, +{"mtummcr2", XSPR(31,467,769), XSPR_MASK, POWER9, 0, {RS}}, +{"mtmmcr2", XSPR(31,467,769), XSPR_MASK, POWER9, 0, {RS}}, +{"mtummcra", XSPR(31,467,770), XSPR_MASK, POWER9, 0, {RS}}, {"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, 0, {RS}}, {"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, 0, {RS}}, {"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, 0, {RS}}, {"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, 0, {RS}}, {"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, 0, {RS}}, {"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, 0, {RS}}, +{"mtummcr0", XSPR(31,467,779), XSPR_MASK, POWER9, 0, {RS}}, +{"mtsier", XSPR(31,467,784), XSPR_MASK, POWER10, 0, {RS}}, +{"mtmmcra", XSPR(31,467,786), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpmc1", XSPR(31,467,787), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpmc2", XSPR(31,467,788), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpmc3", XSPR(31,467,789), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpmc4", XSPR(31,467,790), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpmc5", XSPR(31,467,791), XSPR_MASK, POWER7, 0, {RS}}, +{"mtpmc6", XSPR(31,467,792), XSPR_MASK, POWER7, 0, {RS}}, +{"mtmmcr0", XSPR(31,467,795), XSPR_MASK, POWER7, 0, {RS}}, +{"mtsiar", XSPR(31,467,796), XSPR_MASK, POWER10, 0, {RS}}, +{"mtsdar", XSPR(31,467,797), XSPR_MASK, POWER10, 0, {RS}}, +{"mtmmcr1", XSPR(31,467,798), XSPR_MASK, POWER7, 0, {RS}}, +{"mtbescrs", XSPR(31,467,800), XSPR_MASK, POWER9, 0, {RS}}, +{"mtbescrsu", XSPR(31,467,801), XSPR_MASK, POWER9, 0, {RS}}, +{"mtbescrr", XSPR(31,467,802), XSPR_MASK, POWER9, 0, {RS}}, +{"mtbescrru", XSPR(31,467,803), XSPR_MASK, POWER9, 0, {RS}}, +{"mtebbhr", XSPR(31,467,804), XSPR_MASK, POWER9, 0, {RS}}, +{"mtebbrr", XSPR(31,467,805), XSPR_MASK, POWER9, 0, {RS}}, +{"mtbescr", XSPR(31,467,806), XSPR_MASK, POWER9, 0, {RS}}, +{"mttar", XSPR(31,467,815), XSPR_MASK, POWER9, 0, {RS}}, +{"mtasdr", XSPR(31,467,816), XSPR_MASK, POWER10, 0, {RS}}, +{"mtpsscr", XSPR(31,467,823), XSPR_MASK, POWER10, 0, {RS}}, +{"mtic", XSPR(31,467,848), XSPR_MASK, POWER8, 0, {RS}}, +{"mtvtb", XSPR(31,467,849), XSPR_MASK, POWER8, 0, {RS}}, +{"mthpsscr", XSPR(31,467,855), XSPR_MASK, POWER10, 0, {RS}}, {"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, 0, {RS}}, {"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, 0, {RS}}, {"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, 0, {RS}}, |