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-rw-r--r--gas/config/tc-loongarch.c3
-rw-r--r--gas/testsuite/gas/loongarch/64_pcrel.d2
-rw-r--r--gas/testsuite/gas/loongarch/imm_ins.d4
-rw-r--r--gas/testsuite/gas/loongarch/imm_ins_32.d2
-rw-r--r--gas/testsuite/gas/loongarch/jmp_op.d12
-rw-r--r--gas/testsuite/gas/loongarch/li.d8
-rw-r--r--gas/testsuite/gas/loongarch/macro_op.d4
-rw-r--r--gas/testsuite/gas/loongarch/macro_op_32.d4
-rw-r--r--gas/testsuite/gas/loongarch/macro_op_large_abs.d12
-rw-r--r--gas/testsuite/gas/loongarch/macro_op_large_pc.d12
-rw-r--r--gas/testsuite/gas/loongarch/nop.d2
-rw-r--r--gas/testsuite/gas/loongarch/relax_align.d6
-rw-r--r--gas/testsuite/gas/loongarch/reloc.d2
-rw-r--r--include/opcode/loongarch.h2
-rw-r--r--ld/testsuite/ld-loongarch-elf/jmp_op.d2
-rw-r--r--ld/testsuite/ld-loongarch-elf/macro_op.d24
-rw-r--r--ld/testsuite/ld-loongarch-elf/macro_op_32.d4
-rw-r--r--ld/testsuite/ld-loongarch-elf/relax-align.dd4
-rw-r--r--opcodes/loongarch-dis.c26
-rw-r--r--opcodes/loongarch-opc.c23
20 files changed, 94 insertions, 64 deletions
diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c
index 7366e76..6e8aa35 100644
--- a/gas/config/tc-loongarch.c
+++ b/gas/config/tc-loongarch.c
@@ -802,7 +802,8 @@ get_loongarch_opcode (struct loongarch_cl_insn *insn)
for (it = ase->opcodes; it->name; it++)
{
if ((!it->include || (it->include && *it->include))
- && (!it->exclude || (it->exclude && !(*it->exclude))))
+ && (!it->exclude || (it->exclude && !(*it->exclude)))
+ && !(it->pinfo & INSN_DIS_ALIAS))
str_hash_insert (ase->name_hash_entry, it->name,
(void *) it, 0);
}
diff --git a/gas/testsuite/gas/loongarch/64_pcrel.d b/gas/testsuite/gas/loongarch/64_pcrel.d
index 6d4654b..66b80a3 100644
--- a/gas/testsuite/gas/loongarch/64_pcrel.d
+++ b/gas/testsuite/gas/loongarch/64_pcrel.d
@@ -7,5 +7,5 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
[ ]+0:[ ]+R_LARCH_64_PCREL[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/imm_ins.d b/gas/testsuite/gas/loongarch/imm_ins.d
index 0ceaead..c588b5e 100644
--- a/gas/testsuite/gas/loongarch/imm_ins.d
+++ b/gas/testsuite/gas/loongarch/imm_ins.d
@@ -8,10 +8,10 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03848c0c[ ]+ori[ ]+\$t0,[ ]+\$zero,[ ]+0x123
+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
[ ]+4:[ ]+15ffe00d[ ]+lu12i.w[ ]+\$t1,[ ]+-256\(0xfff00\)
[ ]+8:[ ]+16001fed[ ]+lu32i.d[ ]+\$t1,[ ]+255\(0xff\)
-[ ]+c:[ ]+02bffc0e[ ]+addi.w[ ]+\$t2,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc0e[ ]+li.w[ ]+\$t2,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1601ffee[ ]+lu32i.d[ ]+\$t2,[ ]+4095\(0xfff\)
[ ]+14:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+18:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
diff --git a/gas/testsuite/gas/loongarch/imm_ins_32.d b/gas/testsuite/gas/loongarch/imm_ins_32.d
index 0a826bf..5fd5835 100644
--- a/gas/testsuite/gas/loongarch/imm_ins_32.d
+++ b/gas/testsuite/gas/loongarch/imm_ins_32.d
@@ -8,7 +8,7 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03848c0c[ ]+ori[ ]+\$t0,[ ]+\$zero,[ ]+0x123
+[ ]+0:[ ]+03848c0c[ ]+li.w[ ]+\$t0,[ ]+0x123
[ ]+4:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+8:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
[ ]+c:[ ]+0009358b[ ]+bytepick.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2
diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d
index a4535c2..0ce804b 100644
--- a/gas/testsuite/gas/loongarch/jmp_op.d
+++ b/gas/testsuite/gas/loongarch/jmp_op.d
@@ -7,12 +7,12 @@
Disassembly of section .text:
00000000.* <.L1>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
-[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
+[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4\(0x3fffc\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+4:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8\(0x3fff8\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+8:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<\.L1>
+[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12\(0x3fff4\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+c:[ ]+R_LARCH_B16[ ]+\.L1
[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16\(0x7ffff0\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+10:[ ]+R_LARCH_B21[ ]+\.L1
@@ -22,7 +22,7 @@ Disassembly of section .text:
[ ]+18:[ ]+R_LARCH_B21[ ]+\.L1
[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28\(0x7fffe4\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+1c:[ ]+R_LARCH_B21[ ]+\.L1
-[ ]+20:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0
+[ ]+20:[ ]+4c000080[ ]+jr[ ]+\$a0
[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36\(0xfffffdc\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+24:[ ]+R_LARCH_B26[ ]+\.L1
[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40\(0xfffffd8\)[ ]+#[ ]+0[ ]+<\.L1>
@@ -47,4 +47,4 @@ Disassembly of section .text:
[ ]+4c:[ ]+R_LARCH_B16[ ]+\.L1
[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80\(0x3ffb0\)[ ]+#[ ]+0[ ]+<\.L1>
[ ]+50:[ ]+R_LARCH_B16[ ]+\.L1
-[ ]+54:[ ]+4c000020[ ]+jirl[ ]+\$zero,[ ]+\$ra,[ ]+0
+[ ]+54:[ ]+4c000020[ ]+ret[ ]+
diff --git a/gas/testsuite/gas/loongarch/li.d b/gas/testsuite/gas/loongarch/li.d
index 2b37784..6f5bcd1 100644
--- a/gas/testsuite/gas/loongarch/li.d
+++ b/gas/testsuite/gas/loongarch/li.d
@@ -8,16 +8,16 @@
Disassembly of section .text:
00000000.* <_start>:
-[ ]+0:[ ]+03803c06[ ]+ori[ ]+\$a2,[ ]+\$zero,[ ]+0xf
+[ ]+0:[ ]+03803c06[ ]+li\.w[ ]+\$a2,[ ]+0xf
[ ]+4:[ ]+1a000005[ ]+pcalau12i[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_HI20[ ]+msg
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+02c000a5[ ]+addi\.d[ ]+\$a1,[ ]+\$a1,[ ]+0
[ ]+8:[ ]+R_LARCH_PCALA_LO12[ ]+msg
[ ]+8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+c:[ ]+03800404[ ]+ori[ ]+\$a0,[ ]+\$zero,[ ]+0x1
-[ ]+10:[ ]+0381000b[ ]+ori[ ]+\$a7,[ ]+\$zero,[ ]+0x40
+[ ]+c:[ ]+03800404[ ]+li\.w[ ]+\$a0,[ ]+0x1
+[ ]+10:[ ]+0381000b[ ]+li\.w[ ]+\$a7,[ ]+0x40
[ ]+14:[ ]+002b0000[ ]+syscall[ ]+0x0
[ ]+18:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+1c:[ ]+0381740b[ ]+ori[ ]+\$a7,[ ]+\$zero,[ ]+0x5d
+[ ]+1c:[ ]+0381740b[ ]+li\.w[ ]+\$a7,[ ]+0x5d
[ ]+20:[ ]+002b0000[ ]+syscall[ ]+0x0
diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d
index 3465d11..3f6518e 100644
--- a/gas/testsuite/gas/loongarch/macro_op.d
+++ b/gas/testsuite/gas/loongarch/macro_op.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.text>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi\.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi\.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+\.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d
index f5a2b54..5ac15fd 100644
--- a/gas/testsuite/gas/loongarch/macro_op_32.d
+++ b/gas/testsuite/gas/loongarch/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_abs.d b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
index f3a3a48..0c49f68 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_abs.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_abs.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -31,7 +31,7 @@ Disassembly of section .text:
[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+28:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -42,7 +42,7 @@ Disassembly of section .text:
[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+3c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -56,7 +56,7 @@ Disassembly of section .text:
[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+58:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -65,7 +65,7 @@ Disassembly of section .text:
[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+6c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -75,7 +75,7 @@ Disassembly of section .text:
[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+80:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
diff --git a/gas/testsuite/gas/loongarch/macro_op_large_pc.d b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
index f3a3a48..0c49f68 100644
--- a/gas/testsuite/gas/loongarch/macro_op_large_pc.d
+++ b/gas/testsuite/gas/loongarch/macro_op_large_pc.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
[ ]+0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+0:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -31,7 +31,7 @@ Disassembly of section .text:
[ ]+24:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+24:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+28:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+28:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+28:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+28:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+2c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -42,7 +42,7 @@ Disassembly of section .text:
[ ]+38:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+38:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+38:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+3c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+3c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+40:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -56,7 +56,7 @@ Disassembly of section .text:
[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLS1
[ ]+54:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+54:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+58:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+58:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+58:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+5c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -65,7 +65,7 @@ Disassembly of section .text:
[ ]+64:[ ]+380c1484[ ]+ldx.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+68:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+68:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+6c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+6c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+6c:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+6c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+70:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -75,7 +75,7 @@ Disassembly of section .text:
[ ]+78:[ ]+00109484[ ]+add.d[ ]+\$a0,[ ]+\$a0,[ ]+\$a1
[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+7c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+80:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+80:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+80:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+80:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+84:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
diff --git a/gas/testsuite/gas/loongarch/nop.d b/gas/testsuite/gas/loongarch/nop.d
index 4cdcc5c..222456e 100644
--- a/gas/testsuite/gas/loongarch/nop.d
+++ b/gas/testsuite/gas/loongarch/nop.d
@@ -7,4 +7,4 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero, \$zero, 0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d
index 8a44573..1810eb4 100644
--- a/gas/testsuite/gas/loongarch/relax_align.d
+++ b/gas/testsuite/gas/loongarch/relax_align.d
@@ -14,10 +14,10 @@ Disassembly of section .text:
[ ]+4:[ ]+02c00084[ ]+addi\.d[ ]+\$a0,[ ]+\$a0,[ ]+0
[ ]+4:[ ]+R_LARCH_PCALA_LO12[ ]+L1
[ ]+4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+8:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+8:[ ]+03400000[ ]+nop[ ]+
[ ]+8:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc
-[ ]+c:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
-[ ]+10:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+c:[ ]+03400000[ ]+nop[ ]+
+[ ]+10:[ ]+03400000[ ]+nop[ ]+
[ ]+14:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+14:[ ]+R_LARCH_PCALA_HI20[ ]+L1
[ ]+14:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/gas/testsuite/gas/loongarch/reloc.d b/gas/testsuite/gas/loongarch/reloc.d
index 6f5f110..c3820c5 100644
--- a/gas/testsuite/gas/loongarch/reloc.d
+++ b/gas/testsuite/gas/loongarch/reloc.d
@@ -8,7 +8,7 @@
Disassembly of section .text:
00000000.* <.text>:
-[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0
+[ ]+0:[ ]+03400000[ ]+nop[ ]+
[ ]+4:[ ]+58000085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x4
[ ]+4:[ ]+R_LARCH_B16[ ]+.L1
[ ]+8:[ ]+5c000085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+0[ ]+#[ ]+0x8
diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index aa2f3fb..60812fb 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -120,6 +120,8 @@ dec2 : [1-9][0-9]?
const unsigned long pinfo;
#define USELESS 0x0l
+/* Instruction is a simple alias only for disassembler use. */
+#define INSN_DIS_ALIAS 0x00000001l
};
struct hash_control;
diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d
index 09f8910..be82907 100644
--- a/ld/testsuite/ld-loongarch-elf/jmp_op.d
+++ b/ld/testsuite/ld-loongarch-elf/jmp_op.d
@@ -1,5 +1,5 @@
#as:
-#objdump: -dr
+#objdump: -dr -M no-aliases
.*:[ ]+file format .*
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d
index 2649f63..c7f332e 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op.d
@@ -8,9 +8,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
@@ -26,7 +26,7 @@ Disassembly of section .text:
[ ]+20:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+20:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+20:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+24:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+24:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+24:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+24:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+28:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -43,7 +43,7 @@ Disassembly of section .text:
[ ]+3c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+3c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+3c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+40:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+40:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+40:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+40:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+44:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -60,7 +60,7 @@ Disassembly of section .text:
[ ]+58:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+58:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+5c:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+5c:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+5c:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+5c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+60:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -77,7 +77,7 @@ Disassembly of section .text:
[ ]+74:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+74:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+74:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+78:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+78:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+78:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+78:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+7c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -94,7 +94,7 @@ Disassembly of section .text:
[ ]+90:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+90:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+90:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+94:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+94:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+94:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+94:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+98:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -126,7 +126,7 @@ Disassembly of section .text:
[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+c4:[ ]+R_LARCH_PCALA_HI20[ ]+.L1
[ ]+c4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+c8:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+c8:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+c8:[ ]+R_LARCH_PCALA_LO12[ ]+.L1
[ ]+c8:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -143,7 +143,7 @@ Disassembly of section .text:
[ ]+e0:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+e0:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+e0:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
-[ ]+e4:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+e4:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+e4:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1
[ ]+e4:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+e8:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -161,7 +161,7 @@ Disassembly of section .text:
[ ]+100:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+104:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLS1
-[ ]+108:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+108:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+108:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLS1
[ ]+10c:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
[ ]+10c:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLS1
@@ -175,7 +175,7 @@ Disassembly of section .text:
[ ]+11c:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+120:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+120:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLS1
-[ ]+124:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+124:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+124:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+124:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+128:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
@@ -190,7 +190,7 @@ Disassembly of section .text:
[ ]+138:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+13c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+13c:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLS1
-[ ]+140:[ ]+02c00005[ ]+addi.d[ ]+\$a1,[ ]+\$zero,[ ]+0
+[ ]+140:[ ]+02c00005[ ]+li\.d[ ]+\$a1,[ ]+0
[ ]+140:[ ]+R_LARCH_GOT_PC_LO12[ ]+TLS1
[ ]+140:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
[ ]+144:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0
diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
index f5a2b54..5ac15fd 100644
--- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d
+++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d
@@ -9,9 +9,9 @@ Disassembly of section .text:
00000000.* <.L1>:
[ ]+0:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+4:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+4:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+8:[ ]+00150004[ ]+move[ ]+\$a0,[ ]+\$zero
-[ ]+c:[ ]+02bffc04[ ]+addi.w[ ]+\$a0,[ ]+\$zero,[ ]+-1\(0xfff\)
+[ ]+c:[ ]+02bffc04[ ]+li\.w[ ]+\$a0,[ ]+-1\(0xfff\)
[ ]+10:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0
[ ]+10:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1
[ ]+10:[ ]+R_LARCH_RELAX[ ]+\*ABS\*
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align.dd b/ld/testsuite/ld-loongarch-elf/relax-align.dd
index 3149738..5fce225 100644
--- a/ld/testsuite/ld-loongarch-elf/relax-align.dd
+++ b/ld/testsuite/ld-loongarch-elf/relax-align.dd
@@ -1,7 +1,7 @@
#...
.*pcaddi.*
.*pcaddi.*
-.*andi.*
-.*andi.*
+.*nop.*
+.*nop.*
.*0:.*pcaddi.*
#pass
diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c
index 0725270..3a08da1 100644
--- a/opcodes/loongarch-dis.c
+++ b/opcodes/loongarch-dis.c
@@ -25,6 +25,15 @@
#include "libiberty.h"
#include <stdlib.h>
+static bool loongarch_dis_show_aliases = true;
+static const char *const *loongarch_r_disname = NULL;
+static const char *const *loongarch_f_disname = NULL;
+static const char *const *loongarch_fc_disname = NULL;
+static const char *const *loongarch_c_disname = NULL;
+static const char *const *loongarch_cr_disname = NULL;
+static const char *const *loongarch_v_disname = NULL;
+static const char *const *loongarch_x_disname = NULL;
+
static const struct loongarch_opcode *
get_loongarch_opcode_by_binfmt (insn_t insn)
{
@@ -41,7 +50,9 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
{
for (it = ase->opcodes; it->mask; it++)
if (!ase->opc_htab[LARCH_INSN_OPC (it->match)]
- && it->macro == NULL)
+ && it->macro == NULL
+ && (!(it->pinfo & INSN_DIS_ALIAS)
+ || loongarch_dis_show_aliases))
ase->opc_htab[LARCH_INSN_OPC (it->match)] = it;
for (i = 0; i < 16; i++)
if (!ase->opc_htab[i])
@@ -59,14 +70,6 @@ get_loongarch_opcode_by_binfmt (insn_t insn)
return NULL;
}
-static const char *const *loongarch_r_disname = NULL;
-static const char *const *loongarch_f_disname = NULL;
-static const char *const *loongarch_fc_disname = NULL;
-static const char *const *loongarch_c_disname = NULL;
-static const char *const *loongarch_cr_disname = NULL;
-static const char *const *loongarch_v_disname = NULL;
-static const char *const *loongarch_x_disname = NULL;
-
static void
set_default_loongarch_dis_options (void)
{
@@ -89,6 +92,9 @@ set_default_loongarch_dis_options (void)
static int
parse_loongarch_dis_option (const char *option)
{
+ if (strcmp (option, "no-aliases") == 0)
+ loongarch_dis_show_aliases = false;
+
if (strcmp (option, "numeric") == 0)
{
loongarch_r_disname = loongarch_r_normal_name;
@@ -311,6 +317,8 @@ The following LoongArch disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
+ no-aliases Use canonical instruction forms.\n"));
+ fprintf (stream, _("\n\
numeric Print numeric register names, rather than ABI names.\n"));
fprintf (stream, _("\n"));
}
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c
index bd10446..3d1d2c7 100644
--- a/opcodes/loongarch-opc.c
+++ b/opcodes/loongarch-opc.c
@@ -344,9 +344,29 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
};
+static struct loongarch_opcode loongarch_alias_opcodes[] =
+{
+ /* match, mask, name, format, macro, include, exclude, pinfo. */
+ { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* or rd, rj, zero */
+ { 0x02800000, 0xffc003e0, "li.w", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.w rd, zero, simm */
+ { 0x02c00000, 0xffc003e0, "li.d", "r0:5,s10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* addi.d rd, zero, simm */
+ { 0x03400000, 0xffffffff, "nop", "", 0, 0, 0, INSN_DIS_ALIAS }, /* andi zero, zero, 0 */
+ { 0x03800000, 0xffc003e0, "li.w", "r0:5,u10:12", 0, 0, 0, INSN_DIS_ALIAS }, /* ori rd, zero, uimm */
+ /* ret must come before jr because it is more specific. */
+ { 0x4c000020, 0xffffffff, "ret", "", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, ra, 0 */
+ { 0x4c000000, 0xfffffc1f, "jr", "r5:5", 0, 0, 0, INSN_DIS_ALIAS }, /* jirl zero, rj, 0 */
+ { 0x60000000, 0xfc00001f, "bltz", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt rj, zero, offset */
+ { 0x60000000, 0xfc0003e0, "bgtz", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* blt zero, rd, offset */
+ { 0x64000000, 0xfc00001f, "bgez", "r5:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge rj, zero, offset */
+ { 0x64000000, 0xfc0003e0, "blez", "r0:5,sb10:16<<2", 0, 0, 0, INSN_DIS_ALIAS }, /* bge zero, rd, offset */
+ { 0 } /* Terminate the list. */
+};
+
+
static struct loongarch_opcode loongarch_fix_opcodes[] =
{
/* match, mask, name, format, macro, include, exclude, pinfo. */
+ { 0x0, 0x0, "move", "r,r", "or %1,%2,$r0", 0, 0, 0 },
{ 0x00001000, 0xfffffc00, "clo.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00001400, 0xfffffc00, "clz.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00001800, 0xfffffc00, "cto.w", "r0:5,r5:5", 0, 0, 0, 0 },
@@ -367,8 +387,6 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
{ 0x00005400, 0xfffffc00, "bitrev.d", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00005800, 0xfffffc00, "ext.w.h", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00005c00, 0xfffffc00, "ext.w.b", "r0:5,r5:5", 0, 0, 0, 0 },
- /* or %1,%2,$r0 */
- { 0x00150000, 0xfffffc00, "move", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006000, 0xfffffc00, "rdtimel.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006400, 0xfffffc00, "rdtimeh.w", "r0:5,r5:5", 0, 0, 0, 0 },
{ 0x00006800, 0xfffffc00, "rdtime.d", "r0:5,r5:5", 0, 0, 0, 0 },
@@ -2324,6 +2342,7 @@ static struct loongarch_opcode loongarch_lasx_opcodes[] =
struct loongarch_ase loongarch_ASEs[] =
{
{ &LARCH_opts.ase_ilp32, loongarch_macro_opcodes, 0, 0, { 0 }, 0, 0 },
+ { &LARCH_opts.ase_ilp32, loongarch_alias_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_imm_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_privilege_opcodes, 0, 0, { 0 }, 0, 0 },
{ &LARCH_opts.ase_ilp32, loongarch_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
generated by cgit v1.1 at 2024-11-16 03:14:04 +0000