diff options
| -rw-r--r-- | bfd/version.h | 2 | ||||
| -rw-r--r-- | gdb/NEWS | 2 | ||||
| -rw-r--r-- | gdb/alpha-tdep.c | 87 | ||||
| -rw-r--r-- | gdb/doc/gdb.texinfo | 42 | ||||
| -rw-r--r-- | gdb/features/Makefile | 1 | ||||
| -rw-r--r-- | gdb/features/alpha-core.xml | 136 | ||||
| -rw-r--r-- | gdb/features/alpha.c | 111 | ||||
| -rw-r--r-- | gdb/features/alpha.xml | 11 | ||||
| -rw-r--r-- | gdb/testsuite/gdb.arch/amd64-disp-step-avx.exp | 1 |
9 files changed, 353 insertions, 40 deletions
diff --git a/bfd/version.h b/bfd/version.h index 7400e34..a1f72c7 100644 --- a/bfd/version.h +++ b/bfd/version.h @@ -16,7 +16,7 @@ In releases, the date is not included in either version strings or sonames. */ -#define BFD_VERSION_DATE 20250701 +#define BFD_VERSION_DATE 20250703 #define BFD_VERSION @bfd_version@ #define BFD_VERSION_STRING @bfd_version_package@ @bfd_version_string@ #define REPORT_BUGS_TO @report_bugs_to@ @@ -236,6 +236,8 @@ vFile:stat debug information to be disabled at configure time. The flag to do that is --disable-gdb-mdebug-support. +* The Alpha target now supports target descriptions. + *** Changes in GDB 16 * Support for Nios II targets has been removed as this architecture diff --git a/gdb/alpha-tdep.c b/gdb/alpha-tdep.c index 92a6411..5e8a7a0 100644 --- a/gdb/alpha-tdep.c +++ b/gdb/alpha-tdep.c @@ -43,6 +43,9 @@ #include "alpha-tdep.h" #include <algorithm> +#include "target-descriptions.h" +#include "features/alpha.c" + /* Instruction decoding. The notations for registers, immediates and opcodes are the same as the one used in Compaq's Alpha architecture handbook. */ @@ -75,60 +78,38 @@ static const int subq_opcode = 0x10; static const int subq_function = 0x29; -/* Return the name of the REGNO register. +/* Alpha registers using their software names. An empty name corresponds to a register number that used to be used for a virtual register. That virtual register has been removed, but the index is still reserved to maintain compatibility with existing remote alpha targets. */ -static const char * -alpha_register_name (struct gdbarch *gdbarch, int regno) +static const char * const alpha_register_names[] = { - static const char * const register_names[] = - { - "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", - "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", - "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", - "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", - "pc", "", "unique" - }; - - static_assert (ALPHA_NUM_REGS == ARRAY_SIZE (register_names)); - return register_names[regno]; -} + "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", + "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", + "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", + "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "fpcr", + "pc", "", "unique" +}; +static_assert (ALPHA_NUM_REGS == ARRAY_SIZE (alpha_register_names)); static int alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) { - return (strlen (alpha_register_name (gdbarch, regno)) == 0); + return (strlen (alpha_register_names[regno]) == 0); } static int alpha_cannot_store_register (struct gdbarch *gdbarch, int regno) { return (regno == ALPHA_ZERO_REGNUM - || strlen (alpha_register_name (gdbarch, regno)) == 0); -} - -static struct type * -alpha_register_type (struct gdbarch *gdbarch, int regno) -{ - if (regno == ALPHA_SP_REGNUM || regno == ALPHA_GP_REGNUM) - return builtin_type (gdbarch)->builtin_data_ptr; - if (regno == ALPHA_PC_REGNUM) - return builtin_type (gdbarch)->builtin_func_ptr; - - /* Don't need to worry about little vs big endian until - some jerk tries to port to alpha-unicosmk. */ - if (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31) - return builtin_type (gdbarch)->builtin_double; - - return builtin_type (gdbarch)->builtin_int64; + || strlen (alpha_register_names[regno]) == 0); } /* Is REGNUM a member of REGGROUP? */ @@ -1715,11 +1696,39 @@ alpha_software_single_step (struct regcache *regcache) static struct gdbarch * alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) { + tdesc_arch_data_up tdesc_data; + const struct target_desc *tdesc = info.target_desc; + /* Find a candidate among extant architectures. */ arches = gdbarch_list_lookup_by_info (arches, &info); if (arches != NULL) return arches->gdbarch; + if (tdesc == nullptr) + tdesc = tdesc_alpha; + + /* Validate target description. */ + if (tdesc_has_registers (tdesc)) + { + const struct tdesc_feature *feature; + bool valid_p; + + feature = tdesc_find_feature (tdesc, "org.gnu.gdb.alpha.core"); + if (feature == nullptr) + return nullptr; + + tdesc_data = tdesc_data_alloc (); + valid_p = true; + for (int i = 0; i < ALPHA_NUM_REGS; ++i) + valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, + alpha_register_names[i]); + + if (!valid_p) + return nullptr; + } + + gdb_assert (tdesc_data != nullptr); + gdbarch *gdbarch = gdbarch_alloc (&info, gdbarch_tdep_up (new alpha_gdbarch_tdep)); alpha_gdbarch_tdep *tdep = gdbarch_tdep<alpha_gdbarch_tdep> (gdbarch); @@ -1756,8 +1765,7 @@ alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_pc_regnum (gdbarch, ALPHA_PC_REGNUM); set_gdbarch_fp0_regnum (gdbarch, ALPHA_FP0_REGNUM); - set_gdbarch_register_name (gdbarch, alpha_register_name); - set_gdbarch_register_type (gdbarch, alpha_register_type); + tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); set_gdbarch_cannot_fetch_register (gdbarch, alpha_cannot_fetch_register); set_gdbarch_cannot_store_register (gdbarch, alpha_cannot_store_register); @@ -1820,6 +1828,7 @@ INIT_GDB_FILE (alpha_tdep) gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL); + initialize_tdesc_alpha (); /* Let the user set the fence post for heuristic_proc_start. */ /* We really would like to have both "0" and "unlimited" work, but diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index b6d626b..35b770f 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -49237,6 +49237,7 @@ registers using the capitalization used in the description. @menu * AArch64 Features:: +* Alpha Features:: * ARC Features:: * ARM Features:: * i386 Features:: @@ -49543,6 +49544,47 @@ of bytes. Extra registers are allowed in this feature, but they will not affect @value{GDBN}. +@node Alpha Features +@subsection Alpha Features +@cindex target descriptions, Alpha Features + +The @samp{org.gnu.gdb.alpha.core} feature is required for Alpha targets. It +must contain the following 64-bit registers; note that @value{GDBN} uses the +software names for Alpha registers: + +@itemize @minus +@item +@samp{v0}: function return value +@item +@samp{t0} through @samp{t12}: temporary registers +@item +@samp{s0} through @samp{s5}: saved registers +@item +@samp{fp}: frame pointer +@item +@samp{a0} through @samp{a5}: argument registers +@item +@samp{ra}: return address +@item +@samp{at}: assembler temporary register +@item +@samp{gp}: global pointer +@item +@samp{sp}: stack pointer +@item +@samp{zero}: always zero +@item +@samp{f0} through @samp{f30}: floating-point registers +@item +@samp{fpcr}: floating-point control register +@item +@samp{pc}: program counter +@item +@samp{}: an anonymous register for historical purpose +@item +@samp{unique}: PALcode memory slot +@end itemize + @node ARC Features @subsection ARC Features @cindex target descriptions, ARC Features diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 7a8c799..750508a 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -100,6 +100,7 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH)) # --enable-targets=all GDB. You can override this by passing XMLTOC # to make on the command line. XMLTOC = \ + alpha.xml \ microblaze-with-stack-protect.xml \ microblaze.xml \ mips-dsp-linux.xml \ diff --git a/gdb/features/alpha-core.xml b/gdb/features/alpha-core.xml new file mode 100644 index 0000000..c9e12f4 --- /dev/null +++ b/gdb/features/alpha-core.xml @@ -0,0 +1,136 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2025 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.alpha.core"> + <!-- IEEE rounding mode values --> + <enum id="dyn_rm_enum" size="8"> + <!-- Chopped rounding mode --> + <evalue name="chop" value="0"/> + <!-- Minus infinity --> + <evalue name="-inf" value="1"/> + <!-- Normal rounding --> + <evalue name="norm" value="2"/> + <!-- Plus infinity --> + <evalue name="+inf" value="3"/> + </enum> + + <!-- Floating-Point Control Register Flags --> + <flags id="fpcr_flags" size="8"> + <!-- Denormal Operand Exception Disable --> + <field name="DNOD" start="47" end="47"/> + <!-- Denormal Operands to Zero --> + <field name="DNZ" start="48" end="48"/> + <!-- Invalid Operation Disable --> + <field name="INVD" start="49" end="49"/> + <!-- Division by Zero Disable --> + <field name="DZED" start="50" end="50"/> + <!-- Overflow Disable --> + <field name="OVFD" start="51" end="51"/> + <!-- Invalid Operation --> + <field name="INV" start="52" end="52"/> + <!-- Division by Zero --> + <field name="DZE" start="53" end="53"/> + <!-- Overflow --> + <field name="OVF" start="54" end="54"/> + <!-- Underflow --> + <field name="UNF" start="55" end="55"/> + <!-- Inexact Result --> + <field name="INE" start="56" end="56"/> + <!-- Integer Overflow --> + <field name="IOV" start="57" end="57"/> + <!-- Dynamic Rounding Mode --> + <field name="DYN_RM" start="58" end="59" type="dyn_rm_enum"/> + <!-- Underflow to Zero --> + <field name="UNDZ" start="60" end="60"/> + <!-- Underflow Disable --> + <field name="UNFD" start="61" end="61"/> + <!-- Inexact Disable --> + <field name="INED" start="62" end="62"/> + <!-- Summary Bit --> + <field name="SUM" start="63" end="63"/> + </flags> + + <!-- Integer Registers --> + <reg name="v0" bitsize="64" type="int64"/> + <reg name="t0" bitsize="64" type="int64"/> + <reg name="t1" bitsize="64" type="int64"/> + <reg name="t2" bitsize="64" type="int64"/> + <reg name="t3" bitsize="64" type="int64"/> + <reg name="t4" bitsize="64" type="int64"/> + <reg name="t5" bitsize="64" type="int64"/> + <reg name="t6" bitsize="64" type="int64"/> + <reg name="t7" bitsize="64" type="int64"/> + <reg name="s0" bitsize="64" type="int64"/> + <reg name="s1" bitsize="64" type="int64"/> + <reg name="s2" bitsize="64" type="int64"/> + <reg name="s3" bitsize="64" type="int64"/> + <reg name="s4" bitsize="64" type="int64"/> + <reg name="s5" bitsize="64" type="int64"/> + <reg name="fp" bitsize="64" type="int64"/> + <reg name="a0" bitsize="64" type="int64"/> + <reg name="a1" bitsize="64" type="int64"/> + <reg name="a2" bitsize="64" type="int64"/> + <reg name="a3" bitsize="64" type="int64"/> + <reg name="a4" bitsize="64" type="int64"/> + <reg name="a5" bitsize="64" type="int64"/> + <reg name="t8" bitsize="64" type="int64"/> + <reg name="t9" bitsize="64" type="int64"/> + <reg name="t10" bitsize="64" type="int64"/> + <reg name="t11" bitsize="64" type="int64"/> + <reg name="ra" bitsize="64" type="int64"/> + <reg name="t12" bitsize="64" type="int64"/> + <reg name="at" bitsize="64" type="int64"/> + <reg name="gp" bitsize="64" type="data_ptr"/> + <reg name="sp" bitsize="64" type="data_ptr"/> + <reg name="zero" bitsize="64" type="int64" save-restore="no"/> + + <!-- Floating-Point Registers --> + <reg name="f0" bitsize="64" type="float" group="float"/> + <reg name="f1" bitsize="64" type="float" group="float"/> + <reg name="f2" bitsize="64" type="float" group="float"/> + <reg name="f3" bitsize="64" type="float" group="float"/> + <reg name="f4" bitsize="64" type="float" group="float"/> + <reg name="f5" bitsize="64" type="float" group="float"/> + <reg name="f6" bitsize="64" type="float" group="float"/> + <reg name="f7" bitsize="64" type="float" group="float"/> + <reg name="f8" bitsize="64" type="float" group="float"/> + <reg name="f9" bitsize="64" type="float" group="float"/> + <reg name="f10" bitsize="64" type="float" group="float"/> + <reg name="f11" bitsize="64" type="float" group="float"/> + <reg name="f12" bitsize="64" type="float" group="float"/> + <reg name="f13" bitsize="64" type="float" group="float"/> + <reg name="f14" bitsize="64" type="float" group="float"/> + <reg name="f15" bitsize="64" type="float" group="float"/> + <reg name="f16" bitsize="64" type="float" group="float"/> + <reg name="f17" bitsize="64" type="float" group="float"/> + <reg name="f18" bitsize="64" type="float" group="float"/> + <reg name="f19" bitsize="64" type="float" group="float"/> + <reg name="f20" bitsize="64" type="float" group="float"/> + <reg name="f21" bitsize="64" type="float" group="float"/> + <reg name="f22" bitsize="64" type="float" group="float"/> + <reg name="f23" bitsize="64" type="float" group="float"/> + <reg name="f24" bitsize="64" type="float" group="float"/> + <reg name="f25" bitsize="64" type="float" group="float"/> + <reg name="f26" bitsize="64" type="float" group="float"/> + <reg name="f27" bitsize="64" type="float" group="float"/> + <reg name="f28" bitsize="64" type="float" group="float"/> + <reg name="f29" bitsize="64" type="float" group="float"/> + <reg name="f30" bitsize="64" type="float" group="float"/> + + <!-- Floating-Point Control Register --> + <reg name="fpcr" bitsize="64" type="fpcr_flags" group="float"/> + + <!-- Program Counter --> + <reg name="pc" bitsize="64" type="code_ptr"/> + + <!-- Reserved Index for Former Virtual Register --> + <reg name="" bitsize="64" type="int64" save-restore="no"/> + + <!-- PALcode Memory Slot --> + <reg name="unique" bitsize="64" type="int64" group="system"/> +</feature> diff --git a/gdb/features/alpha.c b/gdb/features/alpha.c new file mode 100644 index 0000000..35f12fc --- /dev/null +++ b/gdb/features/alpha.c @@ -0,0 +1,111 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: alpha.xml */ + +#include "osabi.h" +#include "target-descriptions.h" + +const struct target_desc *tdesc_alpha; +static void +initialize_tdesc_alpha (void) +{ + target_desc_up result = allocate_target_description (); + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result.get (), "org.gnu.gdb.alpha.core"); + tdesc_type_with_fields *type_with_fields; + type_with_fields = tdesc_create_enum (feature, "dyn_rm_enum", 8); + tdesc_add_enum_value (type_with_fields, 0, "chop"); + tdesc_add_enum_value (type_with_fields, 1, "-inf"); + tdesc_add_enum_value (type_with_fields, 2, "norm"); + tdesc_add_enum_value (type_with_fields, 3, "+inf"); + + type_with_fields = tdesc_create_flags (feature, "fpcr_flags", 8); + tdesc_add_flag (type_with_fields, 47, "DNOD"); + tdesc_add_flag (type_with_fields, 48, "DNZ"); + tdesc_add_flag (type_with_fields, 49, "INVD"); + tdesc_add_flag (type_with_fields, 50, "DZED"); + tdesc_add_flag (type_with_fields, 51, "OVFD"); + tdesc_add_flag (type_with_fields, 52, "INV"); + tdesc_add_flag (type_with_fields, 53, "DZE"); + tdesc_add_flag (type_with_fields, 54, "OVF"); + tdesc_add_flag (type_with_fields, 55, "UNF"); + tdesc_add_flag (type_with_fields, 56, "INE"); + tdesc_add_flag (type_with_fields, 57, "IOV"); + tdesc_type *field_type; + field_type = tdesc_named_type (feature, "dyn_rm_enum"); + tdesc_add_typed_bitfield (type_with_fields, "DYN_RM", 58, 59, field_type); + tdesc_add_flag (type_with_fields, 60, "UNDZ"); + tdesc_add_flag (type_with_fields, 61, "UNFD"); + tdesc_add_flag (type_with_fields, 62, "INED"); + tdesc_add_flag (type_with_fields, 63, "SUM"); + + tdesc_create_reg (feature, "v0", 0, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t0", 1, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t1", 2, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t2", 3, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t3", 4, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t4", 5, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t5", 6, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t6", 7, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t7", 8, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "s0", 9, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "s1", 10, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "s2", 11, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "s3", 12, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "s4", 13, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "s5", 14, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "fp", 15, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "a0", 16, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "a1", 17, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "a2", 18, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "a3", 19, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "a4", 20, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "a5", 21, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t8", 22, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t9", 23, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t10", 24, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t11", 25, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "ra", 26, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "t12", 27, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "at", 28, 1, NULL, 64, "int64"); + tdesc_create_reg (feature, "gp", 29, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "sp", 30, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "zero", 31, 0, NULL, 64, "int64"); + tdesc_create_reg (feature, "f0", 32, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f1", 33, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f2", 34, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f3", 35, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f4", 36, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f5", 37, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f6", 38, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f7", 39, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f8", 40, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f9", 41, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f10", 42, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f11", 43, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f12", 44, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f13", 45, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f14", 46, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f15", 47, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f16", 48, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f17", 49, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f18", 50, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f19", 51, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f20", 52, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f21", 53, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f22", 54, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f23", 55, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f24", 56, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f25", 57, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f26", 58, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f27", 59, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f28", 60, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f29", 61, 1, "float", 64, "float"); + tdesc_create_reg (feature, "f30", 62, 1, "float", 64, "float"); + tdesc_create_reg (feature, "fpcr", 63, 1, "float", 64, "fpcr_flags"); + tdesc_create_reg (feature, "pc", 64, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "", 65, 0, NULL, 64, "int64"); + tdesc_create_reg (feature, "unique", 66, 1, "system", 64, "int64"); + + tdesc_alpha = result.release (); +} diff --git a/gdb/features/alpha.xml b/gdb/features/alpha.xml new file mode 100644 index 0000000..3ae0ab8 --- /dev/null +++ b/gdb/features/alpha.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2025 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<target version="1.0"> + <xi:include href="alpha-core.xml"/> +</target> diff --git a/gdb/testsuite/gdb.arch/amd64-disp-step-avx.exp b/gdb/testsuite/gdb.arch/amd64-disp-step-avx.exp index 08d73d8..b11efa7 100644 --- a/gdb/testsuite/gdb.arch/amd64-disp-step-avx.exp +++ b/gdb/testsuite/gdb.arch/amd64-disp-step-avx.exp @@ -19,6 +19,7 @@ # instructions. require is_x86_64_m64_target have_avx +require support_displaced_stepping standard_testfile .S |