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| author | Jim Blandy <jimb@codesourcery.com> | 2001-04-12 14:53:20 +0000 |
|---|---|---|
| committer | Jim Blandy <jimb@codesourcery.com> | 2001-04-12 14:53:20 +0000 |
| commit | c0efbca4a368289fc4a8cc9a050668d06c07a46d (patch) | |
| tree | d014b3062f6dea1fc52fc7b76b1879e149764600 /sim | |
| parent | 8cc32590ddd485f534acad9b6a3b792e0c8280bf (diff) | |
| download | binutils-c0efbca4a368289fc4a8cc9a050668d06c07a46d.zip binutils-c0efbca4a368289fc4a8cc9a050668d06c07a46d.tar.gz binutils-c0efbca4a368289fc4a8cc9a050668d06c07a46d.tar.bz2 | |
* mips.igen (CFC1, CTC1): Pass the correct register numbers to
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mips/ChangeLog | 9 | ||||
| -rw-r--r-- | sim/mips/mips.igen | 6 | ||||
| -rw-r--r-- | sim/mips/sim-main.h | 1 |
3 files changed, 12 insertions, 4 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 3ff893a..f03884a 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,12 @@ +2001-04-12 Jim Blandy <jimb@redhat.com> + + * mips.igen (CFC1, CTC1): Pass the correct register numbers to + PENDING_FILL. Use PENDING_SCHED directly to handle the pending + set of the FCSR. + * sim-main.h (COCIDX): Remove definition; this isn't supported by + PENDING_FILL, and you can get the intended effect gracefully by + calling PENDING_SCHED directly. + 2001-02-23 Ben Elliston <bje@redhat.com> * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index f8263f4..03f783a 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -2839,11 +2839,11 @@ if (X) { if (FS == 0) - PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT])); + PENDING_FILL(FCR0IDX,VL4_8(GPR[RT])); else if (FS == 31) - PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT])); + PENDING_FILL(FCR31IDX,VL4_8(GPR[RT])); /* else NOP */ - PENDING_FILL(COCIDX,0); /* special case */ + PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23); } else { /* control from */ diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h index 3ccd4a9..8a1b7f7 100644 --- a/sim/mips/sim-main.h +++ b/sim/mips/sim-main.h @@ -405,7 +405,6 @@ enum float_operation #define Debug (REGISTERS[86]) #define DEPC (REGISTERS[87]) #define EPC (REGISTERS[88]) -#define COCIDX (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */ /* All internal state modified by signal_exception() that may need to be rolled back for passing moment-of-exception image back to gdb. */ |