sim: mips: Add simulator support for mips32r6/mips64r6

2022-02-01  Ali Lown  <ali.lown@imgtec.com>
	    Andrew Bennett  <andrew.bennett@imgtec.com>
	    Dragan Mladjenovic  <dragan.mladjenovic@rt-rk.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/common/ChangeLog:
	* sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21,
	EXTEND26): New macros.

sim/mips/ChangeLog:
	* Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen.
	* configure: Regenerate.
	* configure.ac: Support mipsisa32r6 and mipsisa64r6.
	(sim_engine_run): Pick simulator model from processor specified
	in e_flags.
	* cp1.c (value_fpr): Handle fmt_dc32.
	(fp_unary, fp_binary): Zero initialize locals.
	(update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac,
	fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub):
	New functions.
	(sim_fpu_class_mips_mapping): New.
	* cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define.
	* interp.c (MIPSR6_P): New.
	(load_word): Allow unaligned memory access for MIPSR6.
	* micromips.igen (sc, scd): Adapt to new do_sc* helper signature.
	* mips.igen: Add *r6 models.
	(signal_if_cti, forbiddenslot32): New helpers.
	(delayslot32): Use signal_if_cti.
	(do_sc, do_scd); Add store_ll_bit parameter.
	(sc, scd): Adapt to previous change.
	(nal, beq, bal): New definitions for *r6.
	(sll): Split nop and ssnop cases into ...
	(nop, ssnop): New definitions.
	(loadstore_ea): Use the 32-bit compatibility adressing.
	(cache): Split logic into ...
	(do_cache): New helper.
	(check_fpu): Select IEEE 754-2008 mode for R6.
	(not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add,
	li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd,
	daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra,
	dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr,
	jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror,
	rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav,
	srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt,
	tltu, tne, xor, xori, check_fmt_p, do_load_double,
	do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT,
	cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1,
	dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT,
	mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT,
	sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f,
	bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp,
	tlbr, tlbwi, tlbwr): Enable on *r6 models.
	* mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu,
	dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr,
	wsbh): Likewise.
	* mips3264r6.igen: New file.
	* sim-main.h (FP_formats): Add fmt_dc32.
	(FORBIDDEN_SLOT): New macros.
	(simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines.
	(fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina,
	fp_maxa, fp_fmadd, fp_fmsub): New declarations.
	(R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA,
	MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping
	previous declarations.

sim/testsuite/mips/ChangeLog:
	* basic.exp: Add r6-*.s tests.
	(run_r6_removed_test): New function.
	(run_endian_tests): New function.
	* hilo-hazard-3.s: Skip for mips*r6.
	* r2-fpu.s: New test.
	* r6-64.s: New test.
	* r6-branch.s: New test.
	* r6-forbidden.s: New test.
	* r6-fpu.s: New test.
	* r6-llsc-dp.s: New test.
	* r6-llsc-wp.s: New test.
	* r6-removed.csv: New test.
	* r6-removed.s: New test.
	* r6.s: New test.
	* utils-r6.inc: New inc.

1 files changed, 150 insertions, 0 deletions

diff --git a/sim/testsuite/mips/utils-r6.inc b/sim/testsuite/mips/utils-r6.inc
new file mode 100644
index 0000000..b5c88e5
--- /dev/null
+++ b/sim/testsuite/mips/utils-r6.inc
@@ -0,0 +1,150 @@
+  .macro fp_assert a, b
+  beq \a, \b, 1f
+  nop
+  j _fail
+  nop
+1:
+  .endm
+
+  .macro r6ck_1r inst, a, ret
+  li $4, \a
+  li $6, \ret
+  \inst $7, $4
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_1dr inst, a, ret
+  ld $4, \a
+  ld $6, \ret
+  \inst $7, $4
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_2r inst, a, b, ret
+  li $4, \a
+  li $5, \b
+  li $6, \ret
+  \inst $7, $4, $5
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_2dr inst, a, b, ret
+  ld $4, \a
+  ld $5, \b
+  ld $6, \ret
+  \inst $7, $4, $5
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_2dr1i inst, a, b, imm, ret
+  ld $4, \a
+  ld $5, \b
+  ld $6, \ret
+  \inst $7, $4, $5, \imm
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_1r1i inst, a, imm, ret
+  li $4, \a
+  li $6, \ret
+  \inst $7, $4, \imm
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_1dr1i inst, a, imm, ret
+  ld $4, \a
+  ld $6, \ret
+  \inst $7, $4, \imm
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_0dr1i inst, a, imm, ret
+  ld $4, \a
+  ld $6, \ret
+  \inst $4, $4, \imm
+  fp_assert $6, $4
+  .endm
+
+  .macro r6ck_2r1i inst, a, b, imm, ret
+  li $4, \a
+  li $5, \b
+  li $6, \ret
+  \inst $7, $4, $5, \imm
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_3s inst, a, b, c, ret
+  li $4, \a
+  li $5, \b
+  li $6, \c
+  li $7, \ret
+  mtc1 $4, $f2
+  mtc1 $5, $f4
+  mtc1 $6, $f6
+  \inst $f2, $f4, $f6
+  mfc1 $8, $f2
+  fp_assert $7, $8
+  .endm
+
+  .macro r6ck_2s inst, a, b, ret
+  li $4, \a
+  li $5, \b
+  li $6, \ret
+  mtc1 $4, $f2
+  mtc1 $5, $f4
+  \inst $f2, $f4
+  mfc1 $7, $f2
+  fp_assert $6, $7
+  .endm
+
+  .macro r6ck_2d inst, a, b, ret
+  .data
+1: .dword \a
+2: .dword \b
+3: .dword \ret
+  .text
+  la $4, 1b
+  la $5, 2b
+  la $6, 3b
+  ldc1 $f2, 0($4)
+  ldc1 $f4, 0($5)
+  lw $7, 0($6)
+  lw $8, 4($6)
+  \inst $f2, $f4
+
+  #simulate dmfc1
+  mfhc1 $9, $f2
+  mfc1 $10, $f2
+  fp_assert $7, $9
+  fp_assert $8, $10
+  .endm
+
+  .macro r6ck_3d inst, a, b, c, ret
+  .data
+1: .dword \a
+2: .dword \b
+3: .dword \c
+4: .dword \ret
+  .text
+  la $4, 1b
+  la $5, 2b
+  la $6, 3b
+  la $2, 4b
+  ldc1 $f2, 0($4)
+  ldc1 $f4, 0($5)
+  ldc1 $f6, 0($6)
+  lw $7, 0($2)
+  lw $8, 4($2)
+  \inst $f2, $f4, $f6
+
+  #simulate dmfc1
+  mfhc1 $9, $f2
+  mfc1 $10, $f2
+  fp_assert $7, $9
+  fp_assert $8, $10
+  .endm
+
+.text
+GetPC:
+  move $6, $ra
+  jr $ra