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| author | Jerry Zhang Jian <jerry.zhangjian@sifive.com> | 2025-03-24 22:10:11 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-03-26 10:16:05 +0800 |
| commit | a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf (patch) | |
| tree | c0fc70b70b5e76b154d0e6839f0f9460aa91c32f /sim/testsuite/cris/c/mmap5.c | |
| parent | e5db6129d8d51befe492434d3ebea065cab9adcb (diff) | |
| download | binutils-a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf.zip binutils-a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf.tar.gz binutils-a7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf.tar.bz2 | |
RISC-V: add Smrnmi 1.0 instruction support
Add instruction `mnret' support
Ref:
https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc
https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi
bfd/ChangeLog:
* elfxx-riscv.c: Add new Smrnmi instruction class handling
gas/ChangeLog:
* testsuite/gas/riscv/smrnmi.s: New test for mnret
* testsuite/gas/riscv/rmrnmi.d: Likewise
include/ChangeLog:
* opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET
* opcode/riscv.h: Add new instruction class
opcodes/ChangeLog:
* riscv-opc.c: Add `mnret' instruction
Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
Diffstat (limited to 'sim/testsuite/cris/c/mmap5.c')
0 files changed, 0 insertions, 0 deletions