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authorMike Frysinger <vapier@gentoo.org>2023-12-21 01:36:40 -0500
committerMike Frysinger <vapier@gentoo.org>2023-12-21 01:44:13 -0500
commitc31d7253d2d3bee10388a4908a4bffb0d0011c0a (patch)
treecc28ca86e89a30fbef2ea8c87eb279bf3413910c /sim/rx
parent4935610a577445aef20643a226bca7e6bd11fcb4 (diff)
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sim: rx: add missing break to memory write
It doesn't seem like we want to keep executing the next block of code after processing the request.
Diffstat (limited to 'sim/rx')
-rw-r--r--sim/rx/mem.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/sim/rx/mem.c b/sim/rx/mem.c
index 2cba4cb..83e2302 100644
--- a/sim/rx/mem.c
+++ b/sim/rx/mem.c
@@ -324,6 +324,7 @@ mem_put_byte (unsigned int address, unsigned char value)
halt_pipeline_stats ();
else
reset_pipeline_stats ();
+ break;
}
#endif