2003-06-19 Andrew Cagney <cagney@redhat.com>

	* ld-insn.h: Update copyright.
	(cache_fields): Define.
	(insn_table_fields): Add insn_field_6 and insn_field_7.
	(load_insn_table): Pass in the "cache_rules".
	* ld-insn.c: Update copyright.
	(load_insn_table): Add parameter "cache_rules".  Handle "cache",
	"computed" and "scratch" fields.
	(main): Pass "cache_rules" to load_insn_table.
	* ld-cache.h: Update copyright.
	(append_cache_table): Declare.
	* ld-cache.c: Update copyright.
	(append_cache_table): New function.
	(load_cache_table): Call.
	* gen-model.c: Include "ld-cache.h".
	* gen-itable.c: Include "ld-cache.h".
	* igen.c: Move #include "ld-cache.h" to earlier.  Update
	copyright.
	(main): Permit a NULL "cache_rules".  Pass address of
	"cache_rules" to load_insn_table.
	* Makefile.in (tmp-ld-insn): Add "ld-cache.o".
	(tmp-igen): Do not include ppc-cache-rules.
	(gen-itable.o, gen-model.o): Add "ld-cache.h".
	* ppc-cache-rules: Delete file.
	* ppc-instructions: Add cache rules.

11 files changed, 180 insertions, 95 deletions

diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog
index cd2ab4e..0dd4306 100644
--- a/sim/ppc/ChangeLog
+++ b/sim/ppc/ChangeLog
@@ -1,5 +1,32 @@
 2003-06-19  Andrew Cagney  <cagney@redhat.com>
 
+	* ld-insn.h: Update copyright.
+	(cache_fields): Define.
+	(insn_table_fields): Add insn_field_6 and insn_field_7.
+	(load_insn_table): Pass in the "cache_rules".
+	* ld-insn.c: Update copyright.
+	(load_insn_table): Add parameter "cache_rules".  Handle "cache",
+	"computed" and "scratch" fields.
+	(main): Pass "cache_rules" to load_insn_table.
+	* ld-cache.h: Update copyright.
+	(append_cache_table): Declare.
+	* ld-cache.c: Update copyright.
+	(append_cache_table): New function.
+	(load_cache_table): Call.
+	* gen-model.c: Include "ld-cache.h".
+	* gen-itable.c: Include "ld-cache.h".
+	* igen.c: Move #include "ld-cache.h" to earlier.  Update
+	copyright.
+	(main): Permit a NULL "cache_rules".  Pass address of
+	"cache_rules" to load_insn_table.
+	* Makefile.in (tmp-ld-insn): Add "ld-cache.o".
+	(tmp-igen): Do not include ppc-cache-rules.
+	(gen-itable.o, gen-model.o): Add "ld-cache.h".
+	* ppc-cache-rules: Delete file.
+	* ppc-instructions: Add cache rules.
+
+2003-06-19  Andrew Cagney  <cagney@redhat.com>
+
 	* Makefile.in (ICACHE_CFLAGS, SEMANTICS_CFLAGS): Delete.
 	(SIM_FPU_FLAGS): Define.
 	(icache.o): Delete explicit compile command.
diff --git a/sim/ppc/Makefile.in b/sim/ppc/Makefile.in
index fdaab4d..f8e4b86 100644
--- a/sim/ppc/Makefile.in
+++ b/sim/ppc/Makefile.in
@@ -460,10 +460,9 @@ tmp-dgen: dgen ppc-spr-table $(srcdir)/../../move-if-change
 	touch tmp-dgen
 
 
-tmp-igen: igen ppc-instructions $(IGEN_OPCODE_RULES) ppc-cache-rules $(srcdir)/../../move-if-change tmp-ld-decode tmp-ld-cache tmp-ld-insn tmp-filter
+tmp-igen: igen ppc-instructions $(IGEN_OPCODE_RULES) $(srcdir)/../../move-if-change tmp-ld-decode tmp-ld-cache tmp-ld-insn tmp-filter
 	./igen	$(IGEN_FLAGS) \
 		-o $(srcdir)/$(IGEN_OPCODE_RULES) \
-		-k $(srcdir)/ppc-cache-rules \
 		-I $(srcdir) -i $(srcdir)/ppc-instructions \
 		-n icache.h    -hc tmp-icache.h \
 		-n icache.c    -c  tmp-icache.c \
@@ -534,12 +533,12 @@ tmp-ld-cache: ld-cache.o misc.o lf.o table.o filter_host.o
 ld-insn.o: ld-insn.c misc.h lf.h table.h ld-insn.h ld-decode.h igen.h
 	$(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/ld-insn.c
 tmp-ld-insn: ld-insn.o misc.o lf.o table.o ld-decode.o filter_host.o filter.o
-	$(CC_FOR_BUILD) $(BUILD_CFLAGS) $(BUILD_LDFLAGS) -o tmp-ld-insn -DMAIN $(srcdir)/ld-insn.c misc.o lf.o table.o ld-decode.o filter_host.o filter.o $(BUILD_LIBS)
+	$(CC_FOR_BUILD) $(BUILD_CFLAGS) $(BUILD_LDFLAGS) -o tmp-ld-insn -DMAIN $(srcdir)/ld-insn.c ld-cache.o misc.o lf.o table.o ld-decode.o filter_host.o filter.o $(BUILD_LIBS)
 
-gen-model.o: gen-model.c misc.h lf.h table.h gen-model.h ld-decode.h igen.h ld-insn.h
+gen-model.o: gen-model.c misc.h lf.h table.h gen-model.h ld-decode.h igen.h ld-insn.h ld-cache.h
 	$(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gen-model.c
 
-gen-itable.o: gen-itable.c misc.h lf.h table.h gen-itable.h ld-decode.h igen.h ld-insn.h igen.h
+gen-itable.o: gen-itable.c misc.h lf.h table.h gen-itable.h ld-decode.h igen.h ld-insn.h igen.h ld-cache.h
 	$(CC_FOR_BUILD) $(BUILD_CFLAGS) -c $(srcdir)/gen-itable.c
 
 gen-icache.o: gen-icache.c misc.h lf.h table.h gen-icache.h ld-decode.h igen.h ld-insn.h gen-semantics.h gen-idecode.h
diff --git a/sim/ppc/gen-itable.c b/sim/ppc/gen-itable.c
index 132aa29..4897b98 100644
--- a/sim/ppc/gen-itable.c
+++ b/sim/ppc/gen-itable.c
@@ -26,6 +26,7 @@
 
 #include "filter.h"
 
+#include "ld-cache.h"
 #include "ld-decode.h"
 #include "ld-insn.h"
 
diff --git a/sim/ppc/gen-model.c b/sim/ppc/gen-model.c
index 34c1b90..b461431 100644
--- a/sim/ppc/gen-model.c
+++ b/sim/ppc/gen-model.c
@@ -25,6 +25,7 @@
 
 #include "filter.h"
 
+#include "ld-cache.h"
 #include "ld-decode.h"
 #include "ld-insn.h"
 
diff --git a/sim/ppc/igen.c b/sim/ppc/igen.c
index 464ae87..cc09662 100644
--- a/sim/ppc/igen.c
+++ b/sim/ppc/igen.c
@@ -29,8 +29,8 @@
 
 #include "filter.h"
 
-#include "ld-decode.h"
 #include "ld-cache.h"
+#include "ld-decode.h"
 #include "ld-insn.h"
 
 #include "igen.h"
@@ -480,11 +480,12 @@ main(int argc,
       force_decode_gen_type(optarg);
       break;
     case 'i':
-      if (decode_rules == NULL || cache_rules == NULL) {
-	fprintf(stderr, "Must specify decode and cache tables\n");
+      if (decode_rules == NULL) {
+	fprintf(stderr, "Must specify decode tables\n");
 	exit (1);
       }
-      instructions = load_insn_table(optarg, decode_rules, filters, includes);
+      instructions = load_insn_table(optarg, decode_rules, filters, includes,
+				     &cache_rules);
       fprintf(stderr, "\texpanding ...\n");
       insn_table_expand_insns(instructions);
       break;
diff --git a/sim/ppc/ld-cache.c b/sim/ppc/ld-cache.c
index 135013e..ef16c67 100644
--- a/sim/ppc/ld-cache.c
+++ b/sim/ppc/ld-cache.c
@@ -1,6 +1,6 @@
 /*  This file is part of the program psim.
 
-    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+    Copyright 1994, 1995, 1996, 1997, 2003 Andrew Cagney
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -46,6 +46,24 @@ static const name_map cache_type_map[] = {
 };
 
 
+void
+append_cache_rule (cache_table **table, char *type, char *field_name,
+		   char *derived_name, char *type_def,
+		   char *expression, table_entry *file_entry)
+{
+  while ((*table) != NULL)
+    table = &(*table)->next;
+  (*table) = ZALLOC(cache_table);
+  (*table)->type = name2i(type, cache_type_map);
+  (*table)->field_name = field_name;
+  (*table)->derived_name = derived_name;
+  (*table)->type_def = (strlen(type_def) > 0 ? type_def : NULL);
+  (*table)->expression = (strlen(expression) > 0 ? expression : NULL);
+  (*table)->file_entry = file_entry;
+  (*table)->next = NULL;
+}
+
+
 cache_table *
 load_cache_table(char *file_name,
 		 int hi_bit_nr)
@@ -55,19 +73,13 @@ load_cache_table(char *file_name,
   cache_table *table = NULL;
   cache_table **curr_rule = &table;
   while ((entry = table_entry_read(file)) != NULL) {
-    cache_table *new_rule = ZALLOC(cache_table);
-    new_rule->type = name2i(entry->fields[ca_type], cache_type_map);
-    new_rule->field_name = entry->fields[ca_field_name];
-    new_rule->derived_name = entry->fields[ca_derived_name];
-    new_rule->type_def = (strlen(entry->fields[ca_type_def])
-			  ? entry->fields[ca_type_def]
-			  : NULL);
-    new_rule->expression = (strlen(entry->fields[ca_expression]) > 0
-			    ? entry->fields[ca_expression]
-			    : NULL);
-    new_rule->file_entry = entry;
-    *curr_rule = new_rule;
-    curr_rule = &new_rule->next;
+    append_cache_rule (curr_rule, entry->fields[ca_type],
+		       entry->fields[ca_field_name],
+		       entry->fields[ca_derived_name],
+		       entry->fields[ca_type_def],
+		       entry->fields[ca_expression],
+		       entry);
+    curr_rule = &(*curr_rule)->next;
   }
   return table;
 }
diff --git a/sim/ppc/ld-cache.h b/sim/ppc/ld-cache.h
index 72e3950..a3fd0a4 100644
--- a/sim/ppc/ld-cache.h
+++ b/sim/ppc/ld-cache.h
@@ -1,6 +1,6 @@
 /*  This file is part of the program psim.
 
-    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+    Copyright 1994, 1995, 1996, 1997, 2003, Andrew Cagney
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -79,3 +79,13 @@ struct _cache_table {
 extern cache_table *load_cache_table
 (char *file_name,
  int hi_bit_nr);
+
+extern void append_cache_rule
+(cache_table **table,
+ char *type,
+ char *field_name,
+ char *derived_name,
+ char *type_def,
+ char *expression,
+ table_entry *file_entry);
+
diff --git a/sim/ppc/ld-insn.c b/sim/ppc/ld-insn.c
index 28b6b55..e3b1ba5 100644
--- a/sim/ppc/ld-insn.c
+++ b/sim/ppc/ld-insn.c
@@ -1,6 +1,6 @@
 /*  This file is part of the program psim.
 
-    Copyright (C) 1994,1995,1996, Andrew Cagney <cagney@highland.com.au>
+    Copyright 1994, 1995, 1996, 2003 Andrew Cagney
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -332,7 +332,8 @@ insn_table *
 load_insn_table(const char *file_name,
 		decode_table *decode_rules,
 		filter *filters,
-		table_include *includes)
+		table_include *includes,
+		cache_table **cache_rules)
 {
   table *file = table_open(file_name, nr_insn_table_fields, nr_insn_model_table_fields);
   insn_table *table = ZALLOC(insn_table);
@@ -344,6 +345,33 @@ load_insn_table(const char *file_name,
 	|| it_is("internal", file_entry->fields[insn_flags])) {
       insn_table_insert_function(table, file_entry);
     }
+    else if ((it_is("function", file_entry->fields[insn_form])
+	      || it_is("internal", file_entry->fields[insn_form]))
+	     && !is_filtered_out(file_entry->fields[insn_flags], filters)) {
+      /* Ok, this is evil.  Need to convert a new style function into
+         an old style function.  Construct an old style table and then
+         copy it back.  */
+      char *fields[nr_insn_table_fields];
+      memset (fields, 0, sizeof fields);
+      fields[insn_flags] = file_entry->fields[insn_form];
+      fields[function_type] = file_entry->fields[insn_name];
+      fields[function_name] = file_entry->fields[insn_comment];
+      fields[function_param] = file_entry->fields[insn_field_6];
+      memcpy (file_entry->fields, fields,
+	      sizeof (fields[0]) * file_entry->nr_fields);
+      insn_table_insert_function(table, file_entry);
+#if 0
+      ":" "..."
+       ":" <filter-flags>
+       ":" <filter-models>
+       ":" <typedef>
+       ":" <name>
+       [ ":" <parameter-list> ]
+       <nl>
+       [ <function-model> ]
+       <code-block>
+#endif
+    }	     
     else if (it_is("model", file_entry->fields[insn_flags])) {
       model_table_insert(table, file_entry);
     }
@@ -366,6 +394,18 @@ load_insn_table(const char *file_name,
              && !is_filtered_out(file_entry->fields[insn_flags], filters)) {
       parse_include_entry (file, file_entry, filters, includes);
     }
+    else if ((it_is("cache", file_entry->fields[insn_form])
+	      || it_is("compute", file_entry->fields[insn_form])
+	      || it_is("scratch", file_entry->fields[insn_form]))
+	     && !is_filtered_out(file_entry->fields[insn_flags], filters)) {
+      append_cache_rule (cache_rules,
+			 file_entry->fields[insn_form], /* type */
+			 file_entry->fields[cache_name],
+			 file_entry->fields[cache_derived_name],
+			 file_entry->fields[cache_type_def],
+			 file_entry->fields[cache_expression],
+			 file_entry);
+    }
     else {
       insn_fields *fields;
       /* skip instructions that aren't relevant to the mode */
@@ -930,6 +970,7 @@ main(int argc, char **argv)
   filter *filters = NULL;
   decode_table *decode_rules = NULL;
   insn_table *instructions = NULL;
+  cache_table *cache_rules = NULL;
 
   if (argc != 5)
     error("Usage: insn <filter> <hi-bit-nr> <decode-table> <insn-table>\n");
@@ -938,7 +979,8 @@ main(int argc, char **argv)
   hi_bit_nr = a2i(argv[2]);
   ASSERT(hi_bit_nr < insn_bit_size);
   decode_rules = load_decode_table(argv[3], hi_bit_nr);
-  instructions = load_insn_table(argv[4], decode_rules, filters, NULL);
+  instructions = load_insn_table(argv[4], decode_rules, filters, NULL,
+				 &cache_rules);
   insn_table_expand_insns(instructions);
 
   dump_insn_table(instructions, 0, -1);
diff --git a/sim/ppc/ld-insn.h b/sim/ppc/ld-insn.h
index 06bf838..4e1b7f7 100644
--- a/sim/ppc/ld-insn.h
+++ b/sim/ppc/ld-insn.h
@@ -1,6 +1,6 @@
 /*  This file is part of the program psim.
 
-    Copyright (C) 1994,1995,1996, Andrew Cagney <cagney@highland.com.au>
+    Copyright 1994, 1995, 1996, 2003 Andrew Cagney
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -119,6 +119,8 @@ typedef enum {
   insn_mnemonic,
   insn_name,
   insn_comment,
+  insn_field_6,
+  insn_field_7,
   nr_insn_table_fields
 } insn_table_fields;
 
@@ -139,6 +141,13 @@ typedef enum {
   include_path = insn_name,
 } model_include_fields;
 
+typedef enum {
+  cache_type_def = insn_name,
+  cache_derived_name = insn_comment,
+  cache_name = insn_field_6,
+  cache_expression = insn_field_7,
+} cache_fields;
+
 typedef struct _insn insn;
 struct _insn {
   table_entry *file_entry;
@@ -189,7 +198,8 @@ extern insn_table *load_insn_table
 (const char *file_name,
  decode_table *decode_rules,
  filter *filters,
- table_include *includes);
+ table_include *includes,
+ cache_table **cache_rules);
 
 model *models;
 model *last_model;
diff --git a/sim/ppc/ppc-cache-rules b/sim/ppc/ppc-cache-rules
deleted file mode 100644
index 2b5f472..0000000
--- a/sim/ppc/ppc-cache-rules
+++ /dev/null
@@ -1,65 +0,0 @@
-#
-#   This file is part of the program psim.
-#
-#   Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
-#
-#   This program is free software; you can redistribute it and/or modify
-#   it under the terms of the GNU General Public License as published by
-#   the Free Software Foundation; either version 2 of the License, or
-#   (at your option) any later version.
-#
-#   This program is distributed in the hope that it will be useful,
-#   but WITHOUT ANY WARRANTY; without even the implied warranty of
-#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#   GNU General Public License for more details.
-#
-#   You should have received a copy of the GNU General Public License
-#   along with this program; if not, write to the Free Software
-#   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-#
-cache:RA:RA::
-cache:RA:rA:signed_word *:(cpu_registers(processor)->gpr + RA)
-cache:RA:RA_BITMASK:unsigned32:(1 << RA)
-compute:RA:RA_is_0:int:(RA == 0)
-cache:RT:RT::
-cache:RT:rT:signed_word *:(cpu_registers(processor)->gpr + RT)
-cache:RT:RT_BITMASK:unsigned32:(1 << RT)
-cache:RS:RS::
-cache:RS:rS:signed_word *:(cpu_registers(processor)->gpr + RS)
-cache:RS:RS_BITMASK:unsigned32:(1 << RS)
-cache:RB:RB::
-cache:RB:rB:signed_word *:(cpu_registers(processor)->gpr + RB)
-cache:RB:RB_BITMASK:unsigned32:(1 << RB)
-scratch:FRA:FRA::
-cache:FRA:frA:unsigned64 *:(cpu_registers(processor)->fpr + FRA)
-cache:FRA:FRA_BITMASK:unsigned32:(1 << FRA)
-scratch:FRB:FRB::
-cache:FRB:frB:unsigned64 *:(cpu_registers(processor)->fpr + FRB)
-cache:FRB:FRB_BITMASK:unsigned32:(1 << FRB)
-scratch:FRC:FRC::
-cache:FRC:frC:unsigned64 *:(cpu_registers(processor)->fpr + FRC)
-cache:FRC:FRC_BITMASK:unsigned32:(1 << FRC)
-scratch:FRS:FRS::
-cache:FRS:frS:unsigned64 *:(cpu_registers(processor)->fpr + FRS)
-cache:FRS:FRS_BITMASK:unsigned32:(1 << FRS)
-scratch:FRT:FRT::
-cache:FRT:frT:unsigned64 *:(cpu_registers(processor)->fpr + FRT)
-cache:FRT:FRT_BITMASK:unsigned32:(1 << FRT)
-cache:SI:EXTS_SI:unsigned_word:((signed_word)(signed16)instruction)
-scratch:BI:BI::
-cache:BI:BIT32_BI::BIT32(BI)
-cache:BF:BF::
-cache:BF:BF_BITMASK:unsigned32:(1 << BF)
-scratch:BA:BA::
-cache:BA:BIT32_BA::BIT32(BA)
-cache:BA:BA_BITMASK:unsigned32:(1 << BA)
-scratch:BB:BB::
-cache:BB:BIT32_BB::BIT32(BB)
-cache:BB:BB_BITMASK:unsigned32:(1 << BB)
-cache:BT:BT::
-cache:BT:BT_BITMASK:unsigned32:(1 << BT)
-cache:BD:EXTS_BD_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~3)
-cache:LI:EXTS_LI_0b00:unsigned_word:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3)
-cache:D:EXTS_D:unsigned_word:((signed_word)(signed16)(instruction))
-cache:DS:EXTS_DS_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~0x3)
-#compute:SPR:SPR_is_256:int:(SPR == 256)
diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions
index 6ba0090..d088610 100644
--- a/sim/ppc/ppc-instructions
+++ b/sim/ppc/ppc-instructions
@@ -1,7 +1,7 @@
 #
 #   This file is part of the program psim.
 #
-#   Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+#   Copyright 1994, 1995, 1996, 1997, 2003 Andrew Cagney
 #
 #   --
 #
@@ -33,6 +33,53 @@
 #   along with this program; if not, write to the Free Software
 #   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 #
+
+:cache::::RA:RA:
+:cache:::signed_word *:rA:RA:(cpu_registers(processor)->gpr + RA)
+:cache:::unsigned32:RA_BITMASK:RA:(1 << RA)
+:compute:::int:RA_is_0:RA:(RA == 0)
+:cache::::RT:RT:
+:cache:::signed_word *:rT:RT:(cpu_registers(processor)->gpr + RT)
+:cache:::unsigned32:RT_BITMASK:RT:(1 << RT)
+:cache::::RS:RS:
+:cache:::signed_word *:rS:RS:(cpu_registers(processor)->gpr + RS)
+:cache:::unsigned32:RS_BITMASK:RS:(1 << RS)
+:cache::::RB:RB:
+:cache:::signed_word *:rB:RB:(cpu_registers(processor)->gpr + RB)
+:cache:::unsigned32:RB_BITMASK:RB:(1 << RB)
+:scratch::::FRA:FRA:
+:cache:::unsigned64 *:frA:FRA:(cpu_registers(processor)->fpr + FRA)
+:cache:::unsigned32:FRA_BITMASK:FRA:(1 << FRA)
+:scratch::::FRB:FRB:
+:cache:::unsigned64 *:frB:FRB:(cpu_registers(processor)->fpr + FRB)
+:cache:::unsigned32:FRB_BITMASK:FRB:(1 << FRB)
+:scratch::::FRC:FRC:
+:cache:::unsigned64 *:frC:FRC:(cpu_registers(processor)->fpr + FRC)
+:cache:::unsigned32:FRC_BITMASK:FRC:(1 << FRC)
+:scratch::::FRS:FRS:
+:cache:::unsigned64 *:frS:FRS:(cpu_registers(processor)->fpr + FRS)
+:cache:::unsigned32:FRS_BITMASK:FRS:(1 << FRS)
+:scratch::::FRT:FRT:
+:cache:::unsigned64 *:frT:FRT:(cpu_registers(processor)->fpr + FRT)
+:cache:::unsigned32:FRT_BITMASK:FRT:(1 << FRT)
+:cache:::unsigned_word:EXTS_SI:SI:((signed_word)(signed16)instruction)
+:scratch::::BI:BI:
+:cache::::BIT32_BI:BI:BIT32(BI)
+:cache::::BF:BF:
+:cache:::unsigned32:BF_BITMASK:BF:(1 << BF)
+:scratch::::BA:BA:
+:cache::::BIT32_BA:BA:BIT32(BA)
+:cache:::unsigned32:BA_BITMASK:BA:(1 << BA)
+:scratch::::BB:BB:
+:cache::::BIT32_BB:BB:BIT32(BB)
+:cache:::unsigned32:BB_BITMASK:BB:(1 << BB)
+:cache::::BT:BT:
+:cache:::unsigned32:BT_BITMASK:BT:(1 << BT)
+:cache:::unsigned_word:EXTS_BD_0b00:BD:(((signed_word)(signed16)instruction) & ~3)
+:cache:::unsigned_word:EXTS_LI_0b00:LI:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3)
+:cache:::unsigned_word:EXTS_D:D:((signed_word)(signed16)(instruction))
+:cache:::unsigned_word:EXTS_DS_0b00:DS:(((signed_word)(signed16)instruction) & ~0x3)
+#:compute:::int:SPR_is_256:SPR:(SPR == 256)
 
 # PowerPC models
 ::model:604:ppc604:  PPC_UNIT_BAD,   PPC_UNIT_BAD,   1,  1,  0