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authorAndrew Cagney <cagney@redhat.com>2003-06-22 16:48:12 +0000
committerAndrew Cagney <cagney@redhat.com>2003-06-22 16:48:12 +0000
commit345d88d96ee2f82d2ec0d1c69cd14506b707b945 (patch)
tree77fe7fa191a6afc07968fbe9421257fb5da8c504 /sim/ppc/registers.c
parent70ecf948d924b4fdc84ba07d2f0c0ee141295ef7 (diff)
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2003-06-22 Andrew Cagney <cagney@redhat.com>
Written by matthew green <mrg@redhat.com>, with fixes from Aldy Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and Nick Clifton <nickc@redhat.com>. * ppc-instructions: Include altivec.igen and e500.igen. (model_busy, model_data): Add vr_busy and vscr_busy. (model_trace_release): Trace vr_busy and vscr_busy. (model_new_cycle): Update vr_busy and vscr_busy. (model_make_busy): Update vr_busy and vscr_busy. * registers.c (register_description): Add Altivec and e500 registers. * psim.c (psim_read_register, psim_read_register): Handle Altivec and e500 registers. * ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers. * configure.in (sim_filter): When *altivec* add "av". When *spe* or *simd* add e500. (sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add WITH_E500. * configure: Re-generate. * e500.igen, altivec.igen: New files. * e500_expression.h, altivec_expression.h: New files. * idecode_expression.h: Update copyright. Include "e500_expression.h" and "altivec_expression.h". * e500_registers.h, altivec_registers.h: New files. * registers.h: Update copyright. Include "e500_registers.h" and "altivec_registers.h". (registers): Add Altivec and e500 specific registers. * Makefile.in (IDECODE_H): Add "idecode_e500.h" and "idecode_altivec.h". (REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h". (tmp-igen): Add dependencies on altivec.igen and e500.igen .
Diffstat (limited to 'sim/ppc/registers.c')
-rw-r--r--sim/ppc/registers.c29
1 files changed, 29 insertions, 0 deletions
diff --git a/sim/ppc/registers.c b/sim/ppc/registers.c
index 2181ced..8323601 100644
--- a/sim/ppc/registers.c
+++ b/sim/ppc/registers.c
@@ -150,6 +150,35 @@ register_description(const char reg[])
description.index = spr_ctr;
description.size = sizeof(unsigned_word);
}
+#ifdef WITH_ALTIVEC
+ else if (reg[0] == 'v' && reg[1] == 'r' && are_digits(reg + 2)) {
+ description.type = reg_vr;
+ description.index = atoi(reg+2);
+ description.size = sizeof(vreg);
+ }
+ else if (!strcmp(reg, "vscr")) {
+ description.type = reg_vscr;
+ description.index = 0;
+ description.size = sizeof(vscreg);
+ }
+#endif
+#ifdef WITH_E500
+ else if (reg[0] == 'e' && reg[1] == 'v' && are_digits(reg + 2)) {
+ description.type = reg_evr;
+ description.index = atoi(reg+2);
+ description.size = sizeof(unsigned64);
+ }
+ else if (reg[0] == 'r' && reg[1] == 'h' && are_digits(reg + 2)) {
+ description.type = reg_gprh;
+ description.index = atoi(reg+2);
+ description.size = sizeof(gpreg);
+ }
+ else if (!strcmp(reg, "acc")) {
+ description.type = reg_acc;
+ description.index = 0;
+ description.size = sizeof(unsigned64);
+ }
+#endif
else {
sprs spr = find_spr(reg);
if (spr != nr_of_sprs) {