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| author | Andrew Cagney <cagney@redhat.com> | 1998-11-12 06:42:34 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-11-12 06:42:34 +0000 |
| commit | d1cbd70abba43c47cbbbf759e225bd946538325a (patch) | |
| tree | 8f6c98c595892a4a3ed48c0e3c7b5ba29506b06a /sim/mips/gencode.c | |
| parent | 93db5513ee4fd5bfd3e556638cc1331d8d0a9533 (diff) | |
| download | binutils-d1cbd70abba43c47cbbbf759e225bd946538325a.zip binutils-d1cbd70abba43c47cbbbf759e225bd946538325a.tar.gz binutils-d1cbd70abba43c47cbbbf759e225bd946538325a.tar.bz2 | |
Add configury for mips-lsi-elf target (32 bit MIPS16).
Fix numerous problems with PENDING_* code.
In old gencode simulator, don't double tick each cycle.
Add BREAK instruction to MIPS16 gencode simulator.
Diffstat (limited to 'sim/mips/gencode.c')
| -rw-r--r-- | sim/mips/gencode.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/mips/gencode.c b/sim/mips/gencode.c index 2e5ed28..ca0dad3 100644 --- a/sim/mips/gencode.c +++ b/sim/mips/gencode.c @@ -2717,6 +2717,15 @@ build_instruction (doisa, features, mips16, insn) case BREAK: + if (mips16) + { + printf(" if (STATE & simDELAYSLOT)\n"); + printf(" PC = cia - 2; /* reference the branch instruction */\n"); + printf(" else\n"); + printf(" PC = cia;\n"); + printf(" sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);\n"); + break; + } printf(" unsigned int break_code = instruction & HALT_INSTRUCTION_MASK;\n"); printf(" if ( break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK)\n"); printf(" || break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))\n"); |