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| author | Mike Frysinger <vapier@gentoo.org> | 2022-11-11 23:27:12 +0700 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2022-12-21 22:27:12 -0500 |
| commit | 2011a547790488fb3a8c8e8e33044b61c702339a (patch) | |
| tree | 98666befc2d68232be7c723d659304cd8769e593 /sim/mips/configure | |
| parent | d455df988abbc7b8c29a77f2dfe8439a9ffa8881 (diff) | |
| download | binutils-2011a547790488fb3a8c8e8e33044b61c702339a.zip binutils-2011a547790488fb3a8c8e8e33044b61c702339a.tar.gz binutils-2011a547790488fb3a8c8e8e33044b61c702339a.tar.bz2 | |
sim: mips: match target on cpu settings
We don't need to enforce larger target settings when the only thing
the sim should care about is the CPU target. So reduce most of the
target matches to only check the CPU.
Diffstat (limited to 'sim/mips/configure')
| -rwxr-xr-x | sim/mips/configure | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/sim/mips/configure b/sim/mips/configure index 794c12c..8096368 100755 --- a/sim/mips/configure +++ b/sim/mips/configure @@ -1847,10 +1847,10 @@ case "${target}" in sim_igen_filter="32,f" sim_igen_machine="-M r3900" ;; - mips64vr43*-*-*) sim_gen=IGEN + mips64vr43*) sim_gen=IGEN sim_igen_machine="-M mipsIV" ;; - mips64vr5*-*-*) sim_gen=IGEN + mips64vr5*) sim_gen=IGEN sim_igen_machine="-M vr5000" ;; mips64vr41*) sim_gen=M16 @@ -1859,7 +1859,7 @@ case "${target}" in sim_igen_filter="32,64,f" sim_m16_filter="16" ;; - mips64vr-*-* | mips64vrel-*-*) + mips64vr-* | mips64vrel-*) sim_gen=MULTI sim_multi_configs="\ vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\ @@ -1877,42 +1877,42 @@ case "${target}" in mipsisa64r6:mips64r6:32,64,f:mipsisa32r6,mipsisa64r6" sim_multi_default=mipsisa64r2 ;; - mips64*-*-*) sim_igen_filter="32,64,f" + mips64*) sim_igen_filter="32,64,f" sim_gen=IGEN ;; - mips16*-*-*) sim_gen=M16 + mips16*) sim_gen=M16 sim_igen_filter="32,64,f" sim_m16_filter="16" ;; - mipsisa32r2*-*-*) sim_gen=MULTI + mipsisa32r2*) sim_gen=MULTI sim_multi_configs="\ micromips:micromips32,micromipsdsp:32,f:mips_micromips\ mips32r2:mips32r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2,smartmips:32,f:mipsisa32r2" sim_multi_default=mipsisa32r2 ;; - mipsisa32r6*-*-*) sim_gen=IGEN + mipsisa32r6*) sim_gen=IGEN sim_igen_machine="-M mips32r6" sim_igen_filter="32,f" ;; - mipsisa32*-*-*) sim_gen=M16 + mipsisa32*) sim_gen=M16 sim_igen_machine="-M mips32,mips16,mips16e,smartmips" sim_m16_machine="-M mips16,mips16e,mips32" sim_igen_filter="32,f" ;; - mipsisa64r2*-*-*) sim_gen=M16 + mipsisa64r2*) sim_gen=M16 sim_igen_machine="-M mips64r2,mips3d,mips16,mips16e,mdmx,dsp,dsp2" sim_m16_machine="-M mips16,mips16e,mips64r2" sim_igen_filter="32,64,f" ;; - mipsisa64r6*-*-*) sim_gen=IGEN + mipsisa64r6*) sim_gen=IGEN sim_igen_machine="-M mips64r6" sim_igen_filter="32,64,f" ;; - mipsisa64sb1*-*-*) sim_gen=IGEN + mipsisa64sb1*) sim_gen=IGEN sim_igen_machine="-M mips64,mips3d,sb1" sim_igen_filter="32,64,f" ;; - mipsisa64*-*-*) sim_gen=M16 + mipsisa64*) sim_gen=M16 sim_igen_machine="-M mips64,mips3d,mips16,mips16e,mdmx" sim_m16_machine="-M mips16,mips16e,mips64" sim_igen_filter="32,64,f" @@ -1923,7 +1923,7 @@ case "${target}" in sim_igen_filter="32,f" sim_m16_filter="16" ;; - mips*-*-*) sim_gen=IGEN + mips*) sim_gen=IGEN sim_igen_filter="32,f" ;; esac |