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author | Mike Frysinger <vapier@gentoo.org> | 2015-04-21 02:50:38 -0400 |
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committer | Mike Frysinger <vapier@gentoo.org> | 2015-04-21 03:10:16 -0400 |
commit | e53e5aab53a455c791fff754d72fd17cbbc6b4a8 (patch) | |
tree | d2de33d388b8b371d35b5b7a7080092f08579236 /sim/mcore | |
parent | 767e68f1b93be396e0cf1296a11584dd725b9569 (diff) | |
download | binutils-e53e5aab53a455c791fff754d72fd17cbbc6b4a8.zip binutils-e53e5aab53a455c791fff754d72fd17cbbc6b4a8.tar.gz binutils-e53e5aab53a455c791fff754d72fd17cbbc6b4a8.tar.bz2 |
sim: mcore: drop watchpoint/dumpmem/clearstats support
In preparation for converting to the common memory framework, the custom
commands get in our way. But when we realize that gdb support has been
dropped for mcore, it makes things a bit easier: the main runner does not
let you run arbitrary commands once simulation starts.
So lets disable watchpoint support until it can be converted to the common
watchpoint logic. There's already an ifdef to let us do that.
We straight up drop support for the dumpmem command (no other sim supports
this, and if it's a feature people want, we can add a common func) and the
clearstats command (not a big deal -- just restart your simulation).
We leave in place the verbose check points as a follow up commit will cut
that over to common logic.
Diffstat (limited to 'sim/mcore')
-rw-r--r-- | sim/mcore/ChangeLog | 6 | ||||
-rw-r--r-- | sim/mcore/interp.c | 79 |
2 files changed, 12 insertions, 73 deletions
diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog index 6f49fec..20c6f77 100644 --- a/sim/mcore/ChangeLog +++ b/sim/mcore/ChangeLog @@ -1,5 +1,11 @@ 2015-04-21 Mike Frysinger <vapier@gentoo.org> + * interp.c (WATCHFUNCTIONS): Undef it. + (sim_resume): Move WLhash behind WATCHFUNCTIONS. + (sim_do_command): Delete. + +2015-04-21 Mike Frysinger <vapier@gentoo.org> + * Makefile.in (NL_TARGET): Define. * interp.c (NUM_ELEM, opened, log_open, log_close, is_opened): Delete. (syscall_read_mem, syscall_write_mem): New functions. diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index b7810d2..b837ecf 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -561,7 +561,8 @@ iu_carry (unsigned long a, unsigned long b, int cin) return (x != 0); } -#define WATCHFUNCTIONS 1 +/* TODO: Convert to common watchpoints. */ +#undef WATCHFUNCTIONS #ifdef WATCHFUNCTIONS #define MAXWL 80 @@ -600,7 +601,9 @@ sim_resume (SIM_DESC sd, int step, int siggnal) int insts; int w; int cycs; +#ifdef WATCHFUNCTIONS word WLhash; +#endif cpu.asregs.exception = step ? SIGTRAP: 0; pc = CPU_PC_GET (scpu); @@ -619,11 +622,13 @@ sim_resume (SIM_DESC sd, int step, int siggnal) else cpu.asregs.active_gregs = & cpu.asregs.gregs[0]; +#ifdef WATCHFUNCTIONS /* make a hash to speed exec loop, hope it's nonzero */ WLhash = 0xFFFFFFFF; for (w = 1; w <= ENDWL; w++) WLhash = WLhash & WL[w]; +#endif do { @@ -1889,75 +1894,3 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env) return SIM_RC_OK; } - -void -sim_do_command (SIM_DESC sd, const char *cmd) -{ - /* Nothing there yet; it's all an error. */ - - if (cmd != NULL) - { - char ** simargv = buildargv (cmd); - - if (strcmp (simargv[0], "watch") == 0) - { - if ((simargv[1] == NULL) || (simargv[2] == NULL)) - { - fprintf (stderr, "Error: missing argument to watch cmd.\n"); - freeargv (simargv); - return; - } - - ENDWL++; - - WL[ENDWL] = strtol (simargv[2], NULL, 0); - WLstr[ENDWL] = strdup (simargv[1]); - fprintf (stderr, "Added %s (%x) to watchlist, #%d\n",WLstr[ENDWL], - WL[ENDWL], ENDWL); - - } - else if (strcmp (simargv[0], "dumpmem") == 0) - { - unsigned char * p; - FILE * dumpfile; - - if (simargv[1] == NULL) - fprintf (stderr, "Error: missing argument to dumpmem cmd.\n"); - - fprintf (stderr, "Writing dumpfile %s...",simargv[1]); - - dumpfile = fopen (simargv[1], "w"); - p = cpu.mem; - fwrite (p, cpu.asregs.msize-1, 1, dumpfile); - fclose (dumpfile); - - fprintf (stderr, "done.\n"); - } - else if (strcmp (simargv[0], "clearstats") == 0) - { - cpu.asregs.cycles = 0; - cpu.asregs.insts = 0; - cpu.asregs.stalls = 0; - ENDWL = 0; - } - else if (strcmp (simargv[0], "verbose") == 0) - { - issue_messages = 2; - } - else - { - fprintf (stderr,"Error: \"%s\" is not a valid M.CORE simulator command.\n", - cmd); - } - - freeargv (simargv); - } - else - { - fprintf (stderr, "M.CORE sim commands: \n"); - fprintf (stderr, " watch <funcname> <addr>\n"); - fprintf (stderr, " dumpmem <filename>\n"); - fprintf (stderr, " clearstats\n"); - fprintf (stderr, " verbose\n"); - } -} |