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authorMike Frysinger <vapier@gentoo.org>2015-06-15 19:22:38 +0545
committerMike Frysinger <vapier@gentoo.org>2015-06-17 13:19:51 -0400
commit7d5c6c43ca8a5dd5491f4a58e977ec5501386ee3 (patch)
treebc347f539bd5eb379bd6b8ce9adef4cdff2a9248 /sim/mcore
parent61a0c964e611eaf72489c3049ba206b2f91ea4a9 (diff)
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sim: syscall: add common sim_syscall helpers
Many ports have the same sim syscall logic, so add some helpers to handle all the common details. The arches still have to deal with the unpacking and packing of the syscall arguments, but the rest of the sim<->callback glue is now shared.
Diffstat (limited to 'sim/mcore')
-rw-r--r--sim/mcore/ChangeLog5
-rw-r--r--sim/mcore/interp.c22
2 files changed, 8 insertions, 19 deletions
diff --git a/sim/mcore/ChangeLog b/sim/mcore/ChangeLog
index 389983d..bc1598a 100644
--- a/sim/mcore/ChangeLog
+++ b/sim/mcore/ChangeLog
@@ -1,5 +1,10 @@
2015-06-17 Mike Frysinger <vapier@gentoo.org>
+ * interp.c (handle_trap1): Replace call to cb_syscall with
+ sim_syscall.
+
+2015-06-17 Mike Frysinger <vapier@gentoo.org>
+
* interp.c: Include sim-syscall.h.
(syscall_read_mem, syscall_write_mem): Delete.
(m32r_trap): Change syscall_read_mem/syscall_write_mem
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index e77535b..64d148a 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -203,26 +203,10 @@ set_initial_gprs (SIM_CPU *scpu)
static void
handle_trap1 (SIM_DESC sd)
{
- host_callback *cb = STATE_CALLBACK (sd);
- CB_SYSCALL sc;
-
- CB_SYSCALL_INIT (&sc);
-
- sc.func = cpu.gr[TRAPCODE];
- sc.arg1 = cpu.gr[PARM1];
- sc.arg2 = cpu.gr[PARM2];
- sc.arg3 = cpu.gr[PARM3];
- sc.arg4 = cpu.gr[PARM4];
-
- sc.p1 = (PTR) sd;
- sc.p2 = (PTR) STATE_CPU (sd, 0);
- sc.read_mem = sim_syscall_read_mem;
- sc.write_mem = sim_syscall_write_mem;
-
- cb_syscall (cb, &sc);
-
/* XXX: We don't pass back the actual errno value. */
- cpu.gr[RET1] = sc.result;
+ cpu.gr[RET1] = sim_syscall (STATE_CPU (sd, 0), cpu.gr[TRAPCODE],
+ cpu.gr[PARM1], cpu.gr[PARM2], cpu.gr[PARM3],
+ cpu.gr[PARM4]);
}
static void