* Makefile.in (m32r.o): Depend on cpu.h

	(extract.o): Pass -DSCACHE_P.
	* mloop.in (extract{16,32}): Update call to m32r_decode.
	* arch.h,cpu.h,cpuall.h,decode.[ch]: Regenerate.
	* extract.c,model.c,sem-switch.c,sem.c: Regenerate.
	* sim-main.h: #include "ansidecl.h".
	Don't include cpu-opc.h, done by arch.h.
start-sanitize-m32rx
	* Makefile.in (M32RX_OBJS): Build m32rx support now.
	(m32rx.o): New rule.
	* m32r-sim.h (m32rx_h_cr_[gs]et): Define.
	* m32rx.c (m32rx_{fetch,store}_register): Update {get,set} of PC.
	(m32rx_h_accums_get): New function.
	* mloopx.in: Update call to m32rx_decode.  Rewrite exec loop.
	* cpux.h,decodex.[ch],modelx.c,readx.c,semx.c: Regenerate.
end-sanitize-m32rx

1 files changed, 141 insertions, 168 deletions

diff --git a/sim/m32r/cpux.h b/sim/m32r/cpux.h
index 37332b5..c647d46 100644
--- a/sim/m32r/cpux.h
+++ b/sim/m32r/cpux.h
@@ -1,5 +1,7 @@
 /* CPU family header for m32rx.
 
+This file is machine generated with CGEN.
+
 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of the GNU Simulators.
@@ -50,12 +52,16 @@ typedef struct {
   DI h_accum;
 #define GET_H_ACCUM() CPU (h_accum)
 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
+/* start-sanitize-m32rx */
   /* accumulators */
   DI h_accums[2];
+/* end-sanitize-m32rx */
 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
+/* start-sanitize-m32rx */
   /* abort flag */
   UBI h_abort;
+/* end-sanitize-m32rx */
 #define GET_H_ABORT() CPU (h_abort)
 #define SET_H_ABORT(x) (CPU (h_abort) = (x))
   /* condition bit */
@@ -96,8 +102,7 @@ typedef struct {
 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
 } M32RX_CPU_DATA;
 
-/* FIXME: length parm to decode() is currently unneeded.  */
-extern DECODE *m32rx_decode (SIM_CPU *, insn_t /*, int*/);
+extern DECODE *m32rx_decode (SIM_CPU *, PCADDR, insn_t);
 
 /* The ARGBUF struct.  */
 struct argbuf {
@@ -105,7 +110,9 @@ struct argbuf {
   unsigned int length;
   PCADDR addr;
   const struct cgen_insn *opcode;
-  /* unsigned long insn; - no longer needed */
+#if ! defined (SCACHE_P)
+  insn_t insn;
+#endif
   /* cpu specific data follows */
   union {
     struct { /* e.g. add $dr,$sr */
@@ -240,88 +247,83 @@ struct argbuf {
       UINT f_r1;
       HI f_simm16;
     } fmt_33_ldi16;
-    struct { /* e.g. machi $src1,$src2 */
-      UINT f_r1;
-      UINT f_r2;
-    } fmt_34_machi;
     struct { /* e.g. machi $src1,$src2,$acc */
       UINT f_r1;
       UINT f_acc;
       UINT f_r2;
-    } fmt_35_machi_a;
+    } fmt_34_machi_a;
     struct { /* e.g. mulhi $src1,$src2,$acc */
       UINT f_r1;
       UINT f_acc;
       UINT f_r2;
-    } fmt_36_mulhi_a;
+    } fmt_35_mulhi_a;
     struct { /* e.g. mv $dr,$sr */
       UINT f_r1;
       UINT f_r2;
-    } fmt_37_mv;
-    struct { /* e.g. mvfachi $dr */
-      UINT f_r1;
-    } fmt_38_mvfachi;
+    } fmt_36_mv;
     struct { /* e.g. mvfachi $dr,$accs */
       UINT f_r1;
       UINT f_accs;
-    } fmt_39_mvfachi_a;
+    } fmt_37_mvfachi_a;
     struct { /* e.g. mvfc $dr,$scr */
       UINT f_r1;
       UINT f_r2;
-    } fmt_40_mvfc;
-    struct { /* e.g. mvtachi $src1 */
-      UINT f_r1;
-    } fmt_41_mvtachi;
+    } fmt_38_mvfc;
     struct { /* e.g. mvtachi $src1,$accs */
       UINT f_r1;
       UINT f_accs;
-    } fmt_42_mvtachi_a;
+    } fmt_39_mvtachi_a;
     struct { /* e.g. mvtc $sr,$dcr */
       UINT f_r1;
       UINT f_r2;
-    } fmt_43_mvtc;
+    } fmt_40_mvtc;
     struct { /* e.g. nop */
       int empty;
-    } fmt_44_nop;
-    struct { /* e.g. rac */
-      int empty;
-    } fmt_45_rac;
+    } fmt_41_nop;
     struct { /* e.g. rac $accs */
       UINT f_accs;
-    } fmt_46_rac_a;
-    struct { /* e.g. seth $dr,$hi16 */
+    } fmt_42_rac_a;
+    struct { /* e.g. rte */
+      int empty;
+    } fmt_43_rte;
+    struct { /* e.g. seth $dr,#$hi16 */
       UINT f_r1;
       UHI f_hi16;
-    } fmt_47_seth;
+    } fmt_44_seth;
     struct { /* e.g. slli $dr,#$uimm5 */
       UINT f_r1;
       USI f_uimm5;
-    } fmt_48_slli;
+    } fmt_45_slli;
     struct { /* e.g. st $src1,@($slo16,$src2) */
       UINT f_r1;
       UINT f_r2;
       HI f_simm16;
-    } fmt_49_st_d;
+    } fmt_46_st_d;
     struct { /* e.g. trap #$uimm4 */
       USI f_uimm4;
-    } fmt_50_trap;
+    } fmt_47_trap;
     struct { /* e.g. satb $dr,$src2 */
       UINT f_r1;
       UINT f_r2;
-    } fmt_51_satb;
-    struct { /* e.g. pcmpbz $src2 */
+    } fmt_48_satb;
+    struct { /* e.g. sat $dr,$src2 */
+      UINT f_r1;
       UINT f_r2;
-    } fmt_52_pcmpbz;
+    } fmt_49_sat;
     struct { /* e.g. sadd */
       int empty;
-    } fmt_53_sadd;
+    } fmt_50_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
       UINT f_r1;
       UINT f_r2;
-    } fmt_54_macwu1;
+    } fmt_51_macwu1;
+    struct { /* e.g. msblo $src1,$src2 */
+      UINT f_r1;
+      UINT f_r2;
+    } fmt_52_msblo;
     struct { /* e.g. sc */
       int empty;
-    } fmt_55_sc;
+    } fmt_53_sc;
   } fields;
 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
   unsigned long h_gr_get;
@@ -840,21 +842,7 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_34_MACHI_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_FMT_34_MACHI_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_35_MACHI_A_VARS \
+#define EXTRACT_FMT_34_MACHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -862,7 +850,7 @@ struct scache {
   UINT f_op23; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_35_MACHI_A_CODE \
+#define EXTRACT_FMT_34_MACHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -870,7 +858,7 @@ struct scache {
   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_36_MULHI_A_VARS \
+#define EXTRACT_FMT_35_MULHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -878,7 +866,7 @@ struct scache {
   UINT f_op23; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_36_MULHI_A_CODE \
+#define EXTRACT_FMT_35_MULHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -886,35 +874,21 @@ struct scache {
   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_37_MV_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_FMT_37_MV_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_38_MVFACHI_VARS \
+#define EXTRACT_FMT_36_MV_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_38_MVFACHI_CODE \
+#define EXTRACT_FMT_36_MV_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_39_MVFACHI_A_VARS \
+#define EXTRACT_FMT_37_MVFACHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -922,7 +896,7 @@ struct scache {
   UINT f_accs; \
   UINT f_op3; \
   unsigned int length;
-#define EXTRACT_FMT_39_MVFACHI_A_CODE \
+#define EXTRACT_FMT_37_MVFACHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -930,35 +904,21 @@ struct scache {
   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 
-#define EXTRACT_FMT_40_MVFC_VARS \
-  /* Instruction fields.  */ \
-  UINT f_op1; \
-  UINT f_r1; \
-  UINT f_op2; \
-  UINT f_r2; \
-  unsigned int length;
-#define EXTRACT_FMT_40_MVFC_CODE \
-  length = 2; \
-  f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
-  f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
-  f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
-
-#define EXTRACT_FMT_41_MVTACHI_VARS \
+#define EXTRACT_FMT_38_MVFC_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_41_MVTACHI_CODE \
+#define EXTRACT_FMT_38_MVFC_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_42_MVTACHI_A_VARS \
+#define EXTRACT_FMT_39_MVTACHI_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -966,7 +926,7 @@ struct scache {
   UINT f_accs; \
   UINT f_op3; \
   unsigned int length;
-#define EXTRACT_FMT_42_MVTACHI_A_CODE \
+#define EXTRACT_FMT_39_MVTACHI_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -974,65 +934,65 @@ struct scache {
   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 
-#define EXTRACT_FMT_43_MVTC_VARS \
+#define EXTRACT_FMT_40_MVTC_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_43_MVTC_CODE \
+#define EXTRACT_FMT_40_MVTC_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_44_NOP_VARS \
+#define EXTRACT_FMT_41_NOP_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_44_NOP_CODE \
+#define EXTRACT_FMT_41_NOP_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_45_RAC_VARS \
+#define EXTRACT_FMT_42_RAC_A_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
-  UINT f_r2; \
+  UINT f_accs; \
+  UINT f_op3; \
   unsigned int length;
-#define EXTRACT_FMT_45_RAC_CODE \
+#define EXTRACT_FMT_42_RAC_A_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
+  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
+  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 
-#define EXTRACT_FMT_46_RAC_A_VARS \
+#define EXTRACT_FMT_43_RTE_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
-  UINT f_accs; \
-  UINT f_op3; \
+  UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_46_RAC_A_CODE \
+#define EXTRACT_FMT_43_RTE_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
-  f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
-  f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_47_SETH_VARS \
+#define EXTRACT_FMT_44_SETH_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -1040,7 +1000,7 @@ struct scache {
   UINT f_r2; \
   UINT f_hi16; \
   unsigned int length;
-#define EXTRACT_FMT_47_SETH_CODE \
+#define EXTRACT_FMT_44_SETH_CODE \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1048,21 +1008,21 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_48_SLLI_VARS \
+#define EXTRACT_FMT_45_SLLI_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_shift_op2; \
   UINT f_uimm5; \
   unsigned int length;
-#define EXTRACT_FMT_48_SLLI_CODE \
+#define EXTRACT_FMT_45_SLLI_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
 
-#define EXTRACT_FMT_49_ST_D_VARS \
+#define EXTRACT_FMT_46_ST_D_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -1070,7 +1030,7 @@ struct scache {
   UINT f_r2; \
   int f_simm16; \
   unsigned int length;
-#define EXTRACT_FMT_49_ST_D_CODE \
+#define EXTRACT_FMT_46_ST_D_CODE \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1078,21 +1038,37 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_50_TRAP_VARS \
+#define EXTRACT_FMT_47_TRAP_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_uimm4; \
   unsigned int length;
-#define EXTRACT_FMT_50_TRAP_CODE \
+#define EXTRACT_FMT_47_TRAP_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_51_SATB_VARS \
+#define EXTRACT_FMT_48_SATB_VARS \
+  /* Instruction fields.  */ \
+  UINT f_op1; \
+  UINT f_r1; \
+  UINT f_op2; \
+  UINT f_r2; \
+  UINT f_uimm16; \
+  unsigned int length;
+#define EXTRACT_FMT_48_SATB_CODE \
+  length = 4; \
+  f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
+  f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
+  f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
+  f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
+  f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
+
+#define EXTRACT_FMT_49_SAT_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
@@ -1100,7 +1076,7 @@ struct scache {
   UINT f_r2; \
   UINT f_uimm16; \
   unsigned int length;
-#define EXTRACT_FMT_51_SATB_CODE \
+#define EXTRACT_FMT_49_SAT_CODE \
   length = 4; \
   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
@@ -1108,56 +1084,56 @@ struct scache {
   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 
-#define EXTRACT_FMT_52_PCMPBZ_VARS \
+#define EXTRACT_FMT_50_SADD_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_52_PCMPBZ_CODE \
+#define EXTRACT_FMT_50_SADD_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_53_SADD_VARS \
+#define EXTRACT_FMT_51_MACWU1_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_53_SADD_CODE \
+#define EXTRACT_FMT_51_MACWU1_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_54_MACWU1_VARS \
+#define EXTRACT_FMT_52_MSBLO_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_54_MACWU1_CODE \
+#define EXTRACT_FMT_52_MSBLO_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 
-#define EXTRACT_FMT_55_SC_VARS \
+#define EXTRACT_FMT_53_SC_VARS \
   /* Instruction fields.  */ \
   UINT f_op1; \
   UINT f_r1; \
   UINT f_op2; \
   UINT f_r2; \
   unsigned int length;
-#define EXTRACT_FMT_55_SC_CODE \
+#define EXTRACT_FMT_53_SC_CODE \
   length = 2; \
   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
@@ -1269,29 +1245,29 @@ struct parallel_exec {
       SI sr;
     } fmt_24_jmp;
     struct { /* e.g. ld $dr,@$sr */
-      UQI h_memory;
+      UQI h_memory_sr;
       SI sr;
     } fmt_25_ld;
     struct { /* e.g. ld $dr,@($slo16,$sr) */
-      UQI h_memory;
+      UQI h_memory_add_WI_sr_slo16;
       HI slo16;
       SI sr;
     } fmt_26_ld_d;
     struct { /* e.g. ldb $dr,@$sr */
-      UQI h_memory;
+      UQI h_memory_sr;
       SI sr;
     } fmt_27_ldb;
     struct { /* e.g. ldb $dr,@($slo16,$sr) */
-      UQI h_memory;
+      UQI h_memory_add_WI_sr_slo16;
       HI slo16;
       SI sr;
     } fmt_28_ldb_d;
     struct { /* e.g. ldh $dr,@$sr */
-      UQI h_memory;
+      UQI h_memory_sr;
       SI sr;
     } fmt_29_ldh;
     struct { /* e.g. ldh $dr,@($slo16,$sr) */
-      UQI h_memory;
+      UQI h_memory_add_WI_sr_slo16;
       HI slo16;
       SI sr;
     } fmt_30_ldh_d;
@@ -1304,85 +1280,82 @@ struct parallel_exec {
     struct { /* e.g. ldi $dr,$slo16 */
       HI slo16;
     } fmt_33_ldi16;
-    struct { /* e.g. machi $src1,$src2 */
-      DI accum;
-      SI src1;
-      SI src2;
-    } fmt_34_machi;
     struct { /* e.g. machi $src1,$src2,$acc */
       DI acc;
       SI src1;
       SI src2;
-    } fmt_35_machi_a;
+    } fmt_34_machi_a;
     struct { /* e.g. mulhi $src1,$src2,$acc */
       SI src1;
       SI src2;
-    } fmt_36_mulhi_a;
+    } fmt_35_mulhi_a;
     struct { /* e.g. mv $dr,$sr */
       SI sr;
-    } fmt_37_mv;
-    struct { /* e.g. mvfachi $dr */
-      DI accum;
-    } fmt_38_mvfachi;
+    } fmt_36_mv;
     struct { /* e.g. mvfachi $dr,$accs */
       DI accs;
-    } fmt_39_mvfachi_a;
+    } fmt_37_mvfachi_a;
     struct { /* e.g. mvfc $dr,$scr */
       SI scr;
-    } fmt_40_mvfc;
-    struct { /* e.g. mvtachi $src1 */
-      DI accum;
-      SI src1;
-    } fmt_41_mvtachi;
+    } fmt_38_mvfc;
     struct { /* e.g. mvtachi $src1,$accs */
       DI accs;
       SI src1;
-    } fmt_42_mvtachi_a;
+    } fmt_39_mvtachi_a;
     struct { /* e.g. mvtc $sr,$dcr */
       SI sr;
-    } fmt_43_mvtc;
+    } fmt_40_mvtc;
     struct { /* e.g. nop */
       int empty;
-    } fmt_44_nop;
-    struct { /* e.g. rac */
-      DI accum;
-    } fmt_45_rac;
+    } fmt_41_nop;
     struct { /* e.g. rac $accs */
       DI accs;
-    } fmt_46_rac_a;
-    struct { /* e.g. seth $dr,$hi16 */
+    } fmt_42_rac_a;
+    struct { /* e.g. rte */
+      UBI h_bcond_0;
+      UBI h_bie_0;
+      SI h_bpc_0;
+      UBI h_bsm_0;
+    } fmt_43_rte;
+    struct { /* e.g. seth $dr,#$hi16 */
       UHI hi16;
-    } fmt_47_seth;
+    } fmt_44_seth;
     struct { /* e.g. slli $dr,#$uimm5 */
       SI dr;
       USI uimm5;
-    } fmt_48_slli;
+    } fmt_45_slli;
     struct { /* e.g. st $src1,@($slo16,$src2) */
       HI slo16;
       SI src1;
       SI src2;
-    } fmt_49_st_d;
+    } fmt_46_st_d;
     struct { /* e.g. trap #$uimm4 */
       USI uimm4;
-    } fmt_50_trap;
+    } fmt_47_trap;
     struct { /* e.g. satb $dr,$src2 */
-      int empty;
-    } fmt_51_satb;
-    struct { /* e.g. pcmpbz $src2 */
-      int empty;
-    } fmt_52_pcmpbz;
+      SI src2;
+    } fmt_48_satb;
+    struct { /* e.g. sat $dr,$src2 */
+      UBI condbit;
+      SI src2;
+    } fmt_49_sat;
     struct { /* e.g. sadd */
-      DI h_accums;
-      DI h_accums;
-    } fmt_53_sadd;
+      DI h_accums_0;
+      DI h_accums_1;
+    } fmt_50_sadd;
     struct { /* e.g. macwu1 $src1,$src2 */
-      DI h_accums;
+      DI h_accums_1;
+      SI src1;
+      SI src2;
+    } fmt_51_macwu1;
+    struct { /* e.g. msblo $src1,$src2 */
+      DI accum;
       SI src1;
       SI src2;
-    } fmt_54_macwu1;
+    } fmt_52_msblo;
     struct { /* e.g. sc */
       UBI condbit;
-    } fmt_55_sc;
+    } fmt_53_sc;
   } operands;
 };