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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:33 +0200 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:33 +0200 |
| commit | 49149d595cfdfa32611b2abba564b9b5d7542c91 (patch) | |
| tree | 2903e8be924e2b7f2937f8018ba6596a325d63cc /sim/m32c | |
| parent | 28b7d4f1c98fe62fb1d8f51c18dddca174820962 (diff) | |
| download | binutils-49149d595cfdfa32611b2abba564b9b5d7542c91.zip binutils-49149d595cfdfa32611b2abba564b9b5d7542c91.tar.gz binutils-49149d595cfdfa32611b2abba564b9b5d7542c91.tar.bz2 | |
MIPS/opcodes: Reorder legacy COP0, COP2, COP3 opcode instructions
Group legacy instructions using the COP0, COP2, COP3 opcodes together
and by their coprocessor number, and move them towards the end of the
opcode table. No functional change.
With the addition of explicit ISA exclusions this is maybe not strictly
necessary anymore as the individual legacy instructions are not supposed
to match ISA levels or CPU implementations that have discarded them or
replaced with a new instruction each, but let's not have them scattered
randomly across blocks of unrelated instruction sets where someone chose
to put them previously. Perhaps they could be put back in alphabetical
order in the main instruction block, but let's leave it for another
occasion.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
COP3 opcode instructions.
Diffstat (limited to 'sim/m32c')
0 files changed, 0 insertions, 0 deletions