* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.

	(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
	(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
	instead of CGEN_INSN_INT.
plus, cgen files: Regenerate.

5 files changed, 37 insertions, 25 deletions

diff --git a/sim/lm32/ChangeLog b/sim/lm32/ChangeLog
index b0eab3b..de8b7bb 100755
--- a/sim/lm32/ChangeLog
+++ b/sim/lm32/ChangeLog
@@ -1,3 +1,10 @@
+2009-11-22  Doug Evans  <dje@sebabeach.org>
+
+	* cpu.h: Regenerate.
+	* cpuall.h: Regenerate.
+	* decode.c: Regenerate.
+	* decode.h: Regenerate.
+
 2009-11-03  Doug Evans  <dje@sebabeach.org>
 
 	* arch.c: Regenerate.
diff --git a/sim/lm32/cpu.h b/sim/lm32/cpu.h
index 8b44fa3..3bb7caf 100644
--- a/sim/lm32/cpu.h
+++ b/sim/lm32/cpu.h
@@ -32,6 +32,12 @@ This file is part of the GNU simulators.
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
diff --git a/sim/lm32/cpuall.h b/sim/lm32/cpuall.h
index 1bd6404..ad1e10c 100644
--- a/sim/lm32/cpuall.h
+++ b/sim/lm32/cpuall.h
@@ -29,7 +29,6 @@ This file is part of the GNU simulators.
 
 #ifdef WANT_CPU_LM32BF
 #include "eng.h"
-#include "cgen-engine.h"
 #include "cpu.h"
 #include "decode.h"
 #endif
diff --git a/sim/lm32/decode.c b/sim/lm32/decode.c
index f7f2506..a5d7e2e 100644
--- a/sim/lm32/decode.c
+++ b/sim/lm32/decode.c
@@ -174,14 +174,14 @@ lm32bf_init_idesc_table (SIM_CPU *cpu)
 
 const IDESC *
 lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
-              CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+              CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
               ARGBUF *abuf)
 {
   /* Result of decoder.  */
   LM32BF_INSN_TYPE itype;
 
   {
-    CGEN_INSN_INT insn = base_insn;
+    CGEN_INSN_WORD insn = base_insn;
 
     {
       unsigned int val = (((insn >> 26) & (63 << 0)));
@@ -361,7 +361,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_add:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_user.f
     UINT f_r0;
     UINT f_r1;
@@ -384,7 +384,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_addi:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -407,7 +407,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andi:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_andi.f
     UINT f_r0;
     UINT f_r1;
@@ -430,7 +430,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_andhii:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_andi.f
     UINT f_r0;
     UINT f_r1;
@@ -453,7 +453,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_b:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_be.f
     UINT f_r0;
 
@@ -470,7 +470,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_bi:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bi.f
     SI f_call;
 
@@ -487,7 +487,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_be:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_be.f
     UINT f_r0;
     UINT f_r1;
@@ -510,7 +510,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_call:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_be.f
     UINT f_r0;
 
@@ -527,7 +527,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_calli:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_bi.f
     SI f_call;
 
@@ -544,7 +544,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_divu:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_user.f
     UINT f_r0;
     UINT f_r1;
@@ -567,7 +567,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lb:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -590,7 +590,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lh:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -613,7 +613,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_lw:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -636,7 +636,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_ori:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_andi.f
     UINT f_r0;
     UINT f_r1;
@@ -659,7 +659,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_rcsr:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_rcsr.f
     UINT f_csr;
     UINT f_r2;
@@ -679,7 +679,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sb:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -702,7 +702,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sextb:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_user.f
     UINT f_r0;
     UINT f_r2;
@@ -722,7 +722,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sh:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -745,7 +745,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_sw:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_addi.f
     UINT f_r0;
     UINT f_r1;
@@ -768,7 +768,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_user:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_user.f
     UINT f_r0;
     UINT f_r1;
@@ -794,7 +794,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
  extract_sfmt_wcsr:
   {
     const IDESC *idesc = &lm32bf_insn_data[itype];
-    CGEN_INSN_INT insn = entire_insn;
+    CGEN_INSN_WORD insn = entire_insn;
 #define FLD(f) abuf->fields.sfmt_wcsr.f
     UINT f_csr;
     UINT f_r1;
diff --git a/sim/lm32/decode.h b/sim/lm32/decode.h
index 5327fbf..12d18fd 100644
--- a/sim/lm32/decode.h
+++ b/sim/lm32/decode.h
@@ -26,7 +26,7 @@ This file is part of the GNU simulators.
 #define LM32BF_DECODE_H
 
 extern const IDESC *lm32bf_decode (SIM_CPU *, IADDR,
-                                  CGEN_INSN_INT, CGEN_INSN_INT,
+                                  CGEN_INSN_WORD, CGEN_INSN_WORD,
                                   ARGBUF *);
 extern void lm32bf_init_idesc_table (SIM_CPU *);
 extern void lm32bf_sem_init_idesc_table (SIM_CPU *);