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| author | Mike Frysinger <vapier@gentoo.org> | 2020-12-09 22:26:30 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2021-04-03 16:19:16 -0400 |
| commit | 26da232cbd6dd920da9521e508e42d1a46180ab4 (patch) | |
| tree | 76451bdc21196c61c8c36787c74239660437b777 /sim/example-synacor/README | |
| parent | a389375f5b5fb67acdda6be028526ac44df2fbff (diff) | |
| download | binutils-26da232cbd6dd920da9521e508e42d1a46180ab4.zip binutils-26da232cbd6dd920da9521e508e42d1a46180ab4.tar.gz binutils-26da232cbd6dd920da9521e508e42d1a46180ab4.tar.bz2 | |
sim: example-synacor: a simple implementation for reference
Provide a simple example simulator for people porting to new targets
to use as a reference. This one has the advantage of being used by
people and having a fun program available for it.
It doesn't require a special target -- the example simulators can be
built for any existing port.
Diffstat (limited to 'sim/example-synacor/README')
| -rw-r--r-- | sim/example-synacor/README | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/sim/example-synacor/README b/sim/example-synacor/README new file mode 100644 index 0000000..93ffd53 --- /dev/null +++ b/sim/example-synacor/README @@ -0,0 +1,15 @@ += OVERVIEW = + +The Synacor Challenge is a fun programming exercise with a number of puzzles +built into it. You can find more details about it here: +https://challenge.synacor.com/ + +The first puzzle is writing an interpreter for their custom ISA. This is a +simulator for that custom CPU. The CPU is quite basic: it's 16-bit with only +8 registers and a limited set of instructions. This means the port will never +grow new features. See README.arch-spec for more details. + +Implementing it here ends up being quite useful: it acts as a simple constrained +"real world" example for people who want to implement a new simulator for their +own architecture. We demonstrate all the basic fundamentals (registers, memory, +branches, and tracing) that all ports should have. |