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| author | Mike Frysinger <vapier@gentoo.org> | 2011-06-22 04:21:29 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-06-22 04:21:29 +0000 |
| commit | ce2486ab207e98f04931bc0f562ed4807258344a (patch) | |
| tree | cacfd146f48a530c740e31365d6506db9d32f706 /sim/bfin/ChangeLog | |
| parent | 8eebce8e670072393bc64915348029d68238eee2 (diff) | |
| download | binutils-ce2486ab207e98f04931bc0f562ed4807258344a.zip binutils-ce2486ab207e98f04931bc0f562ed4807258344a.tar.gz binutils-ce2486ab207e98f04931bc0f562ed4807258344a.tar.bz2 | |
sim: bfin: pass up result2/errcode with libgloss syscalls
Now that the Blackfin libgloss code extracts the 2nd result and the
error code from the R1/R2 registers, have the sim fill them up.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/ChangeLog')
| -rw-r--r-- | sim/bfin/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index 92d968a..a504f7a 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,8 @@ +2011-06-22 Mike Frysinger <vapier@gentoo.org> + + * interp.c (bfin_syscall): Delete old comment. Set dreg 1 to + sc.result2 and dreg 2 to sc.errcode. + 2011-06-18 Robin Getz <robin.getz@analog.com> * bfin-sim.c (decode_dsp32shift_0): Clear ASTAT[AV] if val is 0, |