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author | Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk> | 2018-07-24 09:21:44 +0930 |
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committer | Alan Modra <amodra@gmail.com> | 2018-07-26 17:42:47 +0930 |
commit | fa758a70467c37cfe7b261e1dc20d431be3db62e (patch) | |
tree | b2bb47d4a9ab6da95fe2d55e8b9eb4bf9e889a09 /opcodes/ppc-opc.c | |
parent | b358827438360cb5d04fbc59d594583fb506ba65 (diff) | |
download | binutils-fa758a70467c37cfe7b261e1dc20d431be3db62e.zip binutils-fa758a70467c37cfe7b261e1dc20d431be3db62e.tar.gz binutils-fa758a70467c37cfe7b261e1dc20d431be3db62e.tar.bz2 |
PowerPC Improve support for Gekko & Broadway
This is a relatively straightforward patch to improve support for the
IBM Gekko and IBM Broadway processors. Broadway is functionally
equivalent to the IBM 750CL, while Gekko's functionality is a subset
of theirs. The patch simplifies this reality and adds -mgekko and
-mbroadway as aliases for -m750cl. I didn't feel it was worth wasting
a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of
simplified mnemonics for special purpose register access. Notably,
Broadway adds 4 additional IBAT and DBAT registers but these are not
assigned sequential SPR numbers.
gas/
* config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway.
* doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway.
* doc/c-ppc.texi (PowerPC-Opts): Likewise.
* testsuite/gas/ppc/broadway.d,
* testsuite/gas/ppc/broadway.s: New test for broadway.
* testsuite/gas/ppc/ppc.exp: Run new test.
include/
* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
opcodes/
* ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
(powerpc_init_dialect): Handle bfd_mach_ppc_750.
* ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
support disjointed BAT.
(powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
(XSPRGQR_MASK, GEKKO, BROADWAY): Define.
(powerpc_opcodes): Add 750cl extended mnemonics for spr access.
Diffstat (limited to 'opcodes/ppc-opc.c')
-rw-r--r-- | opcodes/ppc-opc.c | 76 |
1 files changed, 71 insertions, 5 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index ba1bd3b..03891a4 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1187,6 +1187,41 @@ extract_spr (uint64_t insn, return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); } +/* Some dialects have 8 [DI]BAT registers instead of the standard 4. */ +#define ALLOW8_BAT (PPC_OPCODE_750) + +static unsigned long +insert_sprbat (unsigned long insn, + long value, + ppc_cpu_t dialect, + const char **errmsg) +{ + if (value > 7 + || (value > 3 && (dialect & ALLOW8_BAT) == 0)) + *errmsg = _("invalid bat number"); + + /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */ + if (value > 3) + value = ((value & 3) << 6) | 1; + else + value = value << 6; + + return insn | (value << 11); +} + +static long +extract_sprbat (unsigned long insn, + ppc_cpu_t dialect, + int *invalid) +{ + unsigned long val = (insn >> 17) & 0x3; + + val = val + ((insn >> 9) & 0x4); + if (val > 3 && (dialect & ALLOW8_BAT) == 0) + *invalid = 1; + return val; +} + /* Some dialects have 8 SPRG registers instead of the standard 4. */ #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) @@ -2305,11 +2340,16 @@ const struct powerpc_operand powerpc_operands[] = /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ #define SPRBAT SPR + 1 -#define SPRBAT_MASK (0x3 << 17) - { 0x3, 17, NULL, NULL, 0 }, +#define SPRBAT_MASK (0xc1 << 11) + { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR }, + + /* The GQR index number in an XFX form m[ft]gqr instruction. */ +#define SPRGQR SPRBAT + 1 +#define SPRGQR_MASK (0x7 << 16) + { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR }, /* The SPRG register number in an XFX form m[ft]sprg instruction. */ -#define SPRG SPRBAT + 1 +#define SPRG SPRGQR + 1 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, /* The SR field in an X form instruction. */ @@ -3366,6 +3406,10 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) /* An XFX form instruction with the SPR field filled in except for the + SPRGQR field. */ +#define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK) + +/* An XFX form instruction with the SPR field filled in except for the SPRG field. */ #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) @@ -3480,6 +3524,8 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define PPC464 PPC440 #define PPC476 PPC_OPCODE_476 #define PPC750 PPC_OPCODE_750 +#define GEKKO PPC_OPCODE_750 +#define BROADWAY PPC_OPCODE_750 #define PPC7450 PPC_OPCODE_7450 #define PPC860 PPC_OPCODE_860 #define PPCPS PPC_OPCODE_PPCPS @@ -3512,7 +3558,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define PPCPMR PPC_OPCODE_PMR #define PPCTMR PPC_OPCODE_TMR #define PPCCHLK PPC_OPCODE_CACHELCK -#define PPCRFMCI PPC_OPCODE_RFMCI +#define PPCRFMCI PPC_OPCODE_RFMCI #define E500MC PPC_OPCODE_E500MC #define PPCA2 PPC_OPCODE_A2 #define TITAN PPC_OPCODE_TITAN @@ -5939,6 +5985,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, 0, {RT}}, {"mfppr", XSPR(31,339,896), XSPR_MASK, POWER7, 0, {RT}}, {"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER7, 0, {RT}}, +{"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, 0, {RT, SPRGQR}}, +{"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, 0, {RT}}, {"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, 0, {RT}}, {"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, 0, {RT}}, {"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, 0, {RT}}, @@ -5983,10 +6034,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, 0, {RT}}, {"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, 0, {RT}}, {"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, 0, {RT}}, +{"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, 0, {RT}}, {"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, 0, {RT}}, +{"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, 0, {RT}}, +{"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, 0, {RT}}, {"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, 0, {RS}}, {"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, 0, {RT}}, {"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, 0, {RT}}, +{"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, 0, {RT}}, {"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, 0, {RT}}, {"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, 0, {RT}}, {"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, 0, {RT}}, @@ -6269,6 +6325,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, 0, {RS}}, {"mtppr", XSPR(31,467,896), XSPR_MASK, POWER7, 0, {RS}}, {"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER7, 0, {RS}}, +{"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, 0, {SPRGQR, RS}}, +{"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, 0, {RS}}, +{"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, 0, {RS}}, +{"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, 0, {RS}}, +{"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, 0, {RS}}, {"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, 0, {RS}}, {"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, 0, {RS}}, {"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, 0, {RS}}, @@ -6309,10 +6370,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, 0, {RS}}, {"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, 0, {RS}}, {"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, 0, {RS}}, -{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, +{"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, 0, {RS}}, +{"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, 0, {RS}}, {"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, 0, {RS}}, +{"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, 0, {RS}}, +{"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, 0, {RS}}, +{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, 0, {RS}}, {"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, 0, {RS}}, {"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, 0, {RS}}, +{"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, 0, {RS}}, {"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, 0, {RS}}, {"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, 0, {RS}}, {"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, 0, {RS}}, |