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| author | Ian Lance Taylor <ian@airs.com> | 1997-09-24 17:09:48 +0000 |
|---|---|---|
| committer | Ian Lance Taylor <ian@airs.com> | 1997-09-24 17:09:48 +0000 |
| commit | d97a8f952c04fc227baff6d65338e854b4f3308f (patch) | |
| tree | fc5f486466c1c954d85cc7b3b9d86b38de722134 /opcodes/m68k-opc.c | |
| parent | fdfabd68a2ffd26d2dac542539f5e61780cf942a (diff) | |
| download | binutils-d97a8f952c04fc227baff6d65338e854b4f3308f.zip binutils-d97a8f952c04fc227baff6d65338e854b4f3308f.tar.gz binutils-d97a8f952c04fc227baff6d65338e854b4f3308f.tar.bz2 | |
* m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr
for mcf5200.
Diffstat (limited to 'opcodes/m68k-opc.c')
| -rw-r--r-- | opcodes/m68k-opc.c | 45 |
1 files changed, 42 insertions, 3 deletions
diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c index f635c6c..08b5d26 100644 --- a/opcodes/m68k-opc.c +++ b/opcodes/m68k-opc.c @@ -294,17 +294,37 @@ const struct m68k_opcode m68k_opcodes[] = {"dbvs", one(0054710), one(0177770), "DsBw", m68000up }, {"divsw", one(0100700), one(0170700), ";wDd", m68000up }, +/* start-sanitize-coldfire */ +{"divsw", one(0100700), one(0170700), ";wDd", m68000up|mcfdiv }, +/* end-sanitize-coldfire */ {"divsl", two(0046100,0006000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divsl", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, +/* start-sanitize-coldfire */ +{"divsl", two(0046100,0004000),two(0177700,0107770),"DsDD", mcfdiv }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"asDD", mcfdiv }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"+sDD", mcfdiv }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"-sDD", mcfdiv }, +{"divsl", two(0046100,0004000),two(0177700,0107770),"dsDD", mcfdiv }, +/* end-sanitize-coldfire */ {"divsll", two(0046100,0004000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divsll", two(0046100,0004000),two(0177700,0107770),";lDD", m68020up|cpu32 }, {"divuw", one(0100300), one(0170700), ";wDd", m68000up }, +/* start-sanitize-coldfire */ +{"divuw", one(0100300), one(0170700), ";wDd", m68000up|mcfdiv }, +/* end-sanitize-coldfire */ {"divul", two(0046100,0002000),two(0177700,0107770),";lD3D1", m68020up|cpu32 }, {"divul", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, +/* start-sanitize-coldfire */ +{"divul", two(0046100,0000000),two(0177700,0107770),"DsDD", mcfdiv }, +{"divul", two(0046100,0000000),two(0177700,0107770),"asDD", mcfdiv }, +{"divul", two(0046100,0000000),two(0177700,0107770),"+sDD", mcfdiv }, +{"divul", two(0046100,0000000),two(0177700,0107770),"-sDD", mcfdiv }, +{"divul", two(0046100,0000000),two(0177700,0107770),"dsDD", mcfdiv }, +/* end-sanitize-coldfire */ {"divull", two(0046100,0000000),two(0177700,0107770),";lD3D1",m68020up|cpu32 }, {"divull", two(0046100,0000000),two(0177700,0107770),";lDD", m68020up|cpu32 }, @@ -1285,7 +1305,7 @@ const struct m68k_opcode m68k_opcodes[] = /* The move opcode can generate the movea and moveq instructions. */ {"moveb", one(0010000), one(0170000), ";b$d", m68000up }, -{"moveb", one(0010000), one(0170000), "ms$d", mcf5200 }, +{"moveb", one(0010000), one(0170000), "ms%d", mcf5200 }, {"moveb", one(0010000), one(0170000), "nspd", mcf5200 }, {"moveb", one(0010000), one(0170000), "obmd", mcf5200 }, @@ -1299,10 +1319,10 @@ const struct m68k_opcode m68k_opcodes[] = {"movew", one(0041300), one(0177770), "CsDs", mcf5200 }, {"movew", one(0042300), one(0177700), ";wCd", m68000up }, {"movew", one(0042300), one(0177700), "DsCd", mcf5200 }, -{"movew", one(0042300), one(0177700), "#wCd", mcf5200 }, +{"movew", one(0042374), one(0177700), "#wCd", mcf5200 }, {"movew", one(0043300), one(0177700), ";wSd", m68000up }, {"movew", one(0043300), one(0177700), "DsSd", mcf5200 }, -{"movew", one(0043300), one(0177700), "#wSd", mcf5200 }, +{"movew", one(0043374), one(0177700), "#wSd", mcf5200 }, {"movel", one(0070000), one(0170400), "MsDd", m68000up | mcf5200 }, {"movel", one(0020000), one(0170000), "*l%d", m68000up }, @@ -1625,6 +1645,20 @@ const struct m68k_opcode m68k_opcodes[] = {"pvalid", two(0xf000, 0x2800), two(0xffc0, 0xffff), "Vs&s", m68851 }, {"pvalid", two(0xf000, 0x2c00), two(0xffc0, 0xfff8), "A3&s", m68851 }, +/* start-sanitize-coldfire */ +{"remsl", two(0046100,0006000),two(0177700,0107770),"DsD3D1", mcfdiv }, +{"remsl", two(0046100,0006000),two(0177700,0107770),"asD3D1", mcfdiv }, +{"remsl", two(0046100,0006000),two(0177700,0107770),"+sD3D1", mcfdiv }, +{"remsl", two(0046100,0006000),two(0177700,0107770),"-sD3D1", mcfdiv }, +{"remsl", two(0046100,0006000),two(0177700,0107770),"dsD3D1", mcfdiv }, + +{"remul", two(0046100,0002000),two(0177700,0107770),"DsD3D1", mcfdiv }, +{"remul", two(0046100,0002000),two(0177700,0107770),"asD3D1", mcfdiv }, +{"remul", two(0046100,0002000),two(0177700,0107770),"+sD3D1", mcfdiv }, +{"remul", two(0046100,0002000),two(0177700,0107770),"-sD3D1", mcfdiv }, +{"remul", two(0046100,0002000),two(0177700,0107770),"dsD3D1", mcfdiv }, +/* end-sanitize-coldfire */ + {"reset", one(0047160), one(0177777), "", m68000up }, {"rolb", one(0160430), one(0170770), "QdDs", m68000up }, @@ -1897,6 +1931,11 @@ const struct m68k_opcode_alias m68k_opcode_aliases[] = { "bhsb", "bccs" }, { "bhsw", "bccw" }, { "bhsl", "bccl" }, + { "blo", "bcsw" }, + { "blos", "bcss" }, + { "blob", "bcss" }, + { "blow", "bcsw" }, + { "blol", "bcsl" }, { "br", "braw", }, { "brs", "bras", }, { "brb", "bras", }, |