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authorJan Beulich <jbeulich@suse.com>2022-07-18 11:20:44 +0200
committerJan Beulich <jbeulich@suse.com>2022-07-18 11:20:44 +0200
commit7e864bf71d55626dce94df26ebaf11f65b4d7b65 (patch)
tree92e7540faf38e783d798f2430f438d1f230ce1b5 /opcodes/i386-tbl.h
parent37cea58867dd1d0df263e82670fd2e7607539d84 (diff)
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x86: correct VMOVSH attributes
Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by suitable means, which would cause #UD). The memory operand form further was using the wrong Masking value, thus allowing zeroing-masking to be encoded for the store form (which would again cause #UD).
Diffstat (limited to 'opcodes/i386-tbl.h')
-rw-r--r--opcodes/i386-tbl.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 6066e5f..b43da35 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -58553,8 +58553,8 @@ const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ "vmovsh", 0x10, 2, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 2, 0, 0,
- 0, 4, 3, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 5, 2, 0, 0,
+ 0, 4, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -58568,7 +58568,7 @@ const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } } } },
{ "vmovsh", 0x10, 3, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 5, 2, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 5, 2, 0, 0,
0, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,