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| author | Jan Beulich <jbeulich@novell.com> | 2018-09-14 11:21:15 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2018-09-14 11:21:15 +0200 |
| commit | 556059dd13a8a9a30b23eacbefbe7b85e74ce7b7 (patch) | |
| tree | 102a1e7fbad887c0dd0c8e8dfd2b03b6aecff27e /opcodes/i386-opc.tbl | |
| parent | bf326452537c11deece2aabe16b6b9d62388a2d9 (diff) | |
| download | binutils-556059dd13a8a9a30b23eacbefbe7b85e74ce7b7.zip binutils-556059dd13a8a9a30b23eacbefbe7b85e74ce7b7.tar.gz binutils-556059dd13a8a9a30b23eacbefbe7b85e74ce7b7.tar.bz2 | |
x86: fold CRC32 templates
Just like other insns having byte and word forms, these can also make
use of the W modifier, which at the same time allows simplifying some
other code a little bit.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 8ce4226..d63dc7e 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1730,12 +1730,8 @@ pcmpistri, 3, 0x6663, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|No_bSuf|No_w pcmpistri, 3, 0x660f3a63, None, 3, CpuSSE4_2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpistrm, 3, 0x6662, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpistrm, 3, 0x660f3a62, None, 3, CpuSSE4_2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -// We put non-8bit version before 8bit so that crc32 with memory operand -// defaults to non-8bit. -crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex, Reg32 } -crc32, 2, 0xf20f38f1, None, 3, CpuSSE4_2|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|NoAVX, { Reg64|Qword|Unspecified|BaseIndex, Reg64 } -crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg8|Byte|Unspecified|BaseIndex, Reg32 } -crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2|Cpu64, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|NoAVX, { Reg8|Byte|Unspecified|BaseIndex, Reg64 } +crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2, W|Modrm|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } +crc32, 2, 0xf20f38f0, None, 3, CpuSSE4_2|Cpu64, W|Modrm|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64|NoAVX, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } // xsave/xrstor New Instructions. |