[PATCH 1/2] Enable Intel AVX512_FP16 instructions

Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.

Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.

gas/

2021-08-05  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>
            Wei Xiao <wei3.xiao@intel.com>
            Lili Cui  <lili.cui@intel.com>

	* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
	(cpu_arch): Add .avx512_fp16.
	(cpu_noarch): Add noavx512_fp16.
	(pte): Add evexmap5 and evexmap6.
	(build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6.
	(check_VecOperations): Handle {1to32}.
	(check_VecOperands): Handle CheckRegNumb.
	(check_word_reg): Handle Toqword.
	(i386_error): Add invalid_dest_and_src_register_set.
	(match_template): Handle invalid_dest_and_src_register_set.
	* doc/c-i386.texi: Document avx512_fp16, noavx512_fp16.

opcodes/

2021-08-05  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>
            Wei Xiao <wei3.xiao@intel.com>
            Lili Cui  <lili.cui@intel.com>

	* i386-dis.c (EXwScalarS): New.
	(EXxh): Ditto.
	(EXxhc): Ditto.
	(EXxmmqh): Ditto.
	(EXxmmqdh): Ditto.
	(EXEvexXwb): Ditto.
	(DistinctDest_Fixup): Ditto.
	(enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode
	and w_swap_mode.
	(enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0,
	PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56,
	PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67,
	PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11,
	PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C,
	PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F,
	PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59,
	PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1,
	PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1,
	PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E,
	PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79,
	PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C,
	PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56,
	PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7
	(enum): Add EVEX_MAP5 and EVEX_MAP6.
	(enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B,
	EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0,
	EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3,
	EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2,
	EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2,
	(get_valid_dis386): Properly handle new instructions.
	(intel_operand_size): Handle new modes.
	(OP_E_memory): Ditto.
	(OP_EX): Ditto.
	* i386-dis-evex.h: Updated for AVX512_FP16.
	* i386-dis-evex-mod.h: Updated for AVX512_FP16.
	* i386-dis-evex-prefix.h: Updated for AVX512_FP16.
	* i386-dis-evex-reg.h : Updated for AVX512_FP16.
	* i386-dis-evex-w.h : Updated for AVX512_FP16.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS,
	and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS
	and CPU_ANY_AVX512BW_FLAGS.
	(cpu_flags): Add CpuAVX512_FP16.
	(opcode_modifiers): Add DistinctDest.
	* i386-opc.h (enum): (AVX512_FP16): New.
	(i386_opcode_modifier): Add reqdistinctreg.
	(i386_cpu_flags): Add cpuavx512_fp16.
	(EVEXMAP5): Defined as a macro.
	(EVEXMAP6): Ditto.
	* i386-opc.tbl: Add Intel AVX512_FP16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Ditto.

1 files changed, 11 insertions, 0 deletions

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 8f0479b..f83af0b 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -211,6 +211,8 @@ enum
   CpuTDX,
   /* Intel AVX VNNI Instructions support required.  */
   CpuAVX_VNNI,
+  /* Intel AVX-512 FP16 Instructions support required.  */
+  CpuAVX512_FP16,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -388,6 +390,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx512_vp2intersect:1;
       unsigned int cputdx:1;
       unsigned int cpuavx_vnni:1;
+      unsigned int cpuavx512_fp16:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
@@ -467,6 +470,9 @@ enum
   Size,
   /* check register size.  */
   CheckRegSize,
+  /* Instrucion requires that destination must be distinct from source
+     registers.  */
+  DistinctDest,
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
 #define IGNORESIZE	1
@@ -578,6 +584,8 @@ enum
      1: 0F opcode prefix / space.
      2: 0F38 opcode prefix / space.
      3: 0F3A opcode prefix / space.
+     5: EVEXMAP5 opcode prefix / space.
+     6: EVEXMAP6 opcode prefix / space.
      8: XOP 08 opcode space.
      9: XOP 09 opcode space.
      A: XOP 0A opcode space.
@@ -586,6 +594,8 @@ enum
 #define SPACE_0F	1
 #define SPACE_0F38	2
 #define SPACE_0F3A	3
+#define SPACE_EVEXMAP5	5
+#define SPACE_EVEXMAP6	6
 #define SPACE_XOP08	8
 #define SPACE_XOP09	9
 #define SPACE_XOP0A	0xA
@@ -718,6 +728,7 @@ typedef struct i386_opcode_modifier
   unsigned int floatr:1;
   unsigned int size:2;
   unsigned int checkregsize:1;
+  unsigned int distinctdest:1;
   unsigned int mnemonicsize:2;
   unsigned int anysize:1;
   unsigned int no_bsuf:1;