diff options
| author | Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> | 2020-10-20 23:56:58 +0530 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-10-20 13:58:04 -0700 |
| commit | 646cc3e0109e4a45a232af8354feafc36c3249ee (patch) | |
| tree | e883bae3df2bdce5f5849c2cf43452d2c838e5ad /opcodes/i386-dis.c | |
| parent | c4464adef2d7909cd45542690b5d3fd6ab1910c6 (diff) | |
| download | binutils-646cc3e0109e4a45a232af8354feafc36c3249ee.zip binutils-646cc3e0109e4a45a232af8354feafc36c3249ee.tar.gz binutils-646cc3e0109e4a45a232af8354feafc36c3249ee.tar.bz2 | |
Add AMD znver3 processor support
gas/
* config/tc-i386.c (cpu_arch): Add CPU_ZNVER3_FLAGS flags.
(i386_align_code): Add PROCESSOR_ZNVER cases.
* doc/c-i386.texi: Add znver3, snp, invlpgb and tlbsync.
* gas/i386/i386.exp: Add new znver3 test cases.
* gas/i386/arch-14-znver3.d: New.
* gas/i386/arch-14.d: New.
* gas/i386/arch-14.s: New.
* gas/i386/invlpgb.d: New.
* gas/i386/invlpgb64.d: New.
* gas/i386/invlpgb.s: New.
* gas/i386/snp.d: New.
* gas/i386/snp64.d: New.
* gas/i386/snp.s: New.
* gas/i386/tlbsync.d: New.
* gas/i386/tlbsync.s: New.
* gas/i386/x86-64-arch-4-znver3.d: New.
* gas/i386/x86-64-arch-4.d: New.
* gas/i386/x86-64-arch-4.s: New.
opcodes/
* i386-dis.c (rm_table): Add tlbsync, snp, invlpgb.
* i386-gen.c (cpu_flag_init): Add new CPU_INVLPGB_FLAGS,
CPU_TLBSYNC_FLAGS, and CPU_SNP_FLAGS.
Add CPU_ZNVER3_FLAGS.
(cpu_flags): Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
* i386-opc.h: Add CpuINVLPGB, CpuTLBSYNC, CpuSNP.
* i386-opc.tbl: Add invlpgb, tlbsync, psmash, pvalidate,
rmpupdate, rmpadjust.
* i386-init.h: Re-generated.
* i386-tbl.h: Re-generated.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 7467ecd..068858b 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -969,6 +969,8 @@ enum PREFIX_0F01_REG_5_MOD_3_RM_6, PREFIX_0F01_REG_5_MOD_3_RM_7, PREFIX_0F01_REG_7_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_6, + PREFIX_0F01_REG_7_MOD_3_RM_7, PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, @@ -1202,6 +1204,9 @@ enum X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, + X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, + X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, + X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, X86_64_0FC7_REG_6_MOD_3_PREFIX_1 }; @@ -3210,6 +3215,22 @@ static const struct dis386 prefix_table[][4] = { { "mcommit", { Skip_MODRM }, 0 }, }, + /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ + { + { "invlpgb", { Skip_MODRM }, 0 }, + { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) }, + }, + + /* PREFIX_0F01_REG_7_MOD_3_RM_7 */ + { + { "tlbsync", { Skip_MODRM }, 0 }, + { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) }, + { Bad_Opcode }, + { "pvalidate", { Skip_MODRM }, 0 }, + }, + /* PREFIX_0F09 */ { { "wbinvd", { XX }, 0 }, @@ -4384,6 +4405,24 @@ static const struct dis386 x86_64_table[][2] = { { "stui", { Skip_MODRM }, 0 }, }, + /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */ + { + { Bad_Opcode }, + { "rmpadjust", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ + { + { Bad_Opcode }, + { "rmpupdate", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */ + { + { Bad_Opcode }, + { "psmash", { Skip_MODRM }, 0 }, + }, + /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ { { Bad_Opcode }, @@ -8990,6 +9029,8 @@ static const struct dis386 rm_table[][8] = { { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, { "clzero", { Skip_MODRM }, 0 }, { "rdpru", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) }, }, { /* RM_0F1E_P_1_MOD_3_REG_7 */ |