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| author | Mike Frysinger <vapier@gentoo.org> | 2011-02-12 19:37:32 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-02-12 19:37:32 +0000 |
| commit | 43a6aa65fe40d7285ea0511f39d32638292e8d35 (patch) | |
| tree | 187c70166c402165700062708d67d89be900b42c /opcodes/bfin-dis.c | |
| parent | 26bb3ddd506a68a8315a4d4215aaff52260fdf95 (diff) | |
| download | binutils-43a6aa65fe40d7285ea0511f39d32638292e8d35.zip binutils-43a6aa65fe40d7285ea0511f39d32638292e8d35.tar.gz binutils-43a6aa65fe40d7285ea0511f39d32638292e8d35.tar.bz2 | |
opcodes: blackfin: drop "GP" register
There never was a "GP" register, so punt it from the decode map. It's
a hold over from a very old processor definition and never made it into
actual silicon.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'opcodes/bfin-dis.c')
| -rw-r--r-- | opcodes/bfin-dis.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index 85b793c..f624bac 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -227,7 +227,7 @@ enum machine_registers REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S, REG_AQ, REG_V, REG_VS, REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0, - REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, + REG_LC1, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP, @@ -262,7 +262,7 @@ static const char * const reg_names[] = "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S", "AQ", "V", "VS", "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0", - "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", + "LC1", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1", "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN", "RETE", "EMUDAT", "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", @@ -423,7 +423,7 @@ static const enum machine_registers decode_allregs[] = REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3, - REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS, + REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_LASTREG, REG_LASTREG, REG_ASTAT, REG_RETS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, |