diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:10 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:10 +0100 |
| commit | abd542a2f1e15303ea4a9bf05d1a937b5162df5e (patch) | |
| tree | 34a1279f78aba258499fe9084f32931339e6452e /opcodes/aarch64-tbl.h | |
| parent | 60336e19658f1b820753ac09797f14b26e594cfa (diff) | |
| download | binutils-abd542a2f1e15303ea4a9bf05d1a937b5162df5e.zip binutils-abd542a2f1e15303ea4a9bf05d1a937b5162df5e.tar.gz binutils-abd542a2f1e15303ea4a9bf05d1a937b5162df5e.tar.bz2 | |
aarch64: Add a _10 suffix to FLD_imm3
SME2 adds various new 3-bit immediate fields, so this patch adds
an lsb position suffix to the name of the field that we already have.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 82f4af2..aa05ca0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5863,7 +5863,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 7-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ "an 8-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \ + Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10), \ "an 8-bit unsigned immediate") \ Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ |