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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:15 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:15 +0100 |
| commit | 5f05951e4b7d0bf5fb21d61d5c52d75ec7d9e985 (patch) | |
| tree | d624fc282ee1da1a575f662ba6c465e7e9da29c3 /opcodes/aarch64-tbl.h | |
| parent | 261f8708dbbb2c0cc1e7be7986083c6a81005b2e (diff) | |
| download | binutils-5f05951e4b7d0bf5fb21d61d5c52d75ec7d9e985.zip binutils-5f05951e4b7d0bf5fb21d61d5c52d75ec7d9e985.tar.gz binutils-5f05951e4b7d0bf5fb21d61d5c52d75ec7d9e985.tar.bz2 | |
aarch64: Add the SME2 CLAMP instructions
FCLAMP, SCLAMP and UCLAMP share the same format, although FCLAMP
doesn't have a .B form.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index cb6f0d6..ce04dff 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5377,6 +5377,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0), SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fclamp", 0xc120c000, 0xff20fc01, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), + SME2_INSN ("fclamp", 0xc120c800, 0xff20fc03, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0), SME2_INSN ("fdot", 0xc1501008, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("fdot", 0xc1509008, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("fdot", 0xc1201000, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), @@ -5522,6 +5524,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0), SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0), SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0), + SME2_INSN ("sclamp", 0xc120c400, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SME2_INSN ("sclamp", 0xc120cc00, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SME2_INSN ("sdot", 0xc1501000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("sdot", 0xc1509000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("sdot", 0xc1601408, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), @@ -5669,6 +5673,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("suvdot", 0xc1508038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), SME2_INSN ("svdot", 0xc1500020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("svdot", 0xc1508020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), + SME2_INSN ("uclamp", 0xc120c401, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SME2_INSN ("uclamp", 0xc120cc01, 0xff20fc03, sme_size_22, 0, OP3 (SME_Zdnx4, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), SME2_INSN ("udot", 0xc1501010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("udot", 0xc1509010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (4), 0), SME2_INSN ("udot", 0xc1601418, 0xfff09c18, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_SHH, F_OD (2), 0), |