Adjust VLE testsuite

To suit f7d69005.

	* testsuite/ld-powerpc/vle-multiseg-1.d: Adjust to suit segment change.
	* testsuite/ld-powerpc/vle-multiseg-2.d: Likewise.
	* testsuite/ld-powerpc/vle-multiseg-3.d: Likewise.
	* testsuite/ld-powerpc/vle-multiseg-6.d: Likewise.
	* testsuite/ld-powerpc/vle-reloc-2.d: Likewise.

6 files changed, 105 insertions, 107 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index dd5fdc1..83fbe7c 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,11 @@
+2016-08-31  Alan Modra  <amodra@gmail.com>
+
+	* testsuite/ld-powerpc/vle-multiseg-1.d: Adjust to suit segment change.
+	* testsuite/ld-powerpc/vle-multiseg-2.d: Likewise.
+	* testsuite/ld-powerpc/vle-multiseg-3.d: Likewise.
+	* testsuite/ld-powerpc/vle-multiseg-6.d: Likewise.
+	* testsuite/ld-powerpc/vle-reloc-2.d: Likewise.
+
 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 
 	* testsuite/ld-arc/tls_gs-01.d: Set to XFAIL on arc*-*-elf*.
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-1.d b/ld/testsuite/ld-powerpc/vle-multiseg-1.d
index d9554a1..17d22bd 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-1.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-1.d
@@ -1,14 +1,12 @@
 
 Elf file type is EXEC.*
 Entry point 0x0
-There are 2 program headers, starting at offset [0-9]+
+There are 1 program headers, starting at offset [0-9]+
 
 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
-  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
-  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
 
  Section to Segment mapping:
   Segment Sections...
-   00     .data 
-   01     .text_vle .text_iv .iv_handlers 
+   00     \.data \.text_vle \.text_iv \.iv_handlers 
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-2.d b/ld/testsuite/ld-powerpc/vle-multiseg-2.d
index 9d83bb5..2b0ca14 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-2.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-2.d
@@ -1,16 +1,12 @@
 
 Elf file type is EXEC.*
 Entry point 0x0
-There are 3 program headers, starting at offset [0-9]+
+There are 1 program headers, starting at offset [0-9]+
 
 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
-  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
-  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
-  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
 
  Section to Segment mapping:
   Segment Sections...
-   00     .text_vle 
-   01     .data 
-   02     .text_iv .iv_handlers 
+   00     \.text_vle \.data \.text_iv \.iv_handlers 
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-3.d b/ld/testsuite/ld-powerpc/vle-multiseg-3.d
index 957b990..c283003 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-3.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-3.d
@@ -1,16 +1,12 @@
 
 Elf file type is EXEC.*
 Entry point 0x0
-There are 3 program headers, starting at offset [0-9]+
+There are 1 program headers, starting at offset [0-9]+
 
 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
-  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
-  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
-  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} RWE 0x[0-f]+
 
  Section to Segment mapping:
   Segment Sections...
-   00     .text_vle .text_iv 
-   01     .data 
-   02     .iv_handlers 
+   00     \.text_vle \.text_iv \.data \.iv_handlers 
diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6.d b/ld/testsuite/ld-powerpc/vle-multiseg-6.d
index 5c3c210..1a4af3e 100644
--- a/ld/testsuite/ld-powerpc/vle-multiseg-6.d
+++ b/ld/testsuite/ld-powerpc/vle-multiseg-6.d
@@ -12,14 +12,14 @@ There are 4 program headers, starting at offset [0-9]+
 
 Program Headers:
   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
-  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+  LOAD ( +0x[0-9a-f]+){5} RW  0x[0-f]+
   LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
   LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
   LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
 
  Section to Segment mapping:
   Segment Sections...
-   00     .data 
-   01     .text_vle 
-   02     .text_iv 
-   03     .text 
+   00     \.data 
+   01     \.text_vle 
+   02     \.text_iv 
+   03     \.text 
diff --git a/ld/testsuite/ld-powerpc/vle-reloc-2.d b/ld/testsuite/ld-powerpc/vle-reloc-2.d
index 1e1c9d4..6baafdc 100644
--- a/ld/testsuite/ld-powerpc/vle-reloc-2.d
+++ b/ld/testsuite/ld-powerpc/vle-reloc-2.d
@@ -2,86 +2,86 @@
 
 Disassembly of section .text:
 
-01800094 <sub1>:
- 1800094:	00 04       	se_blr
-01800096 <sub2>:
- 1800096:	00 04       	se_blr
-01800098 <vle_reloc_2>:
- 1800098:	70 20 c1 c2 	e_or2i  r1,450
- 180009c:	70 40 c1 81 	e_or2i  r2,385
- 18000a0:	70 60 c1 81 	e_or2i  r3,385
- 18000a4:	70 80 c1 ce 	e_or2i  r4,462
- 18000a8:	70 a0 c1 80 	e_or2i  r5,384
- 18000ac:	70 40 c1 81 	e_or2i  r2,385
- 18000b0:	70 20 c9 c2 	e_and2i. r1,450
- 18000b4:	70 40 c9 81 	e_and2i. r2,385
- 18000b8:	70 60 c9 81 	e_and2i. r3,385
- 18000bc:	70 80 c9 ce 	e_and2i. r4,462
- 18000c0:	70 a0 c9 80 	e_and2i. r5,384
- 18000c4:	70 40 c9 81 	e_and2i. r2,385
- 18000c8:	70 20 d1 c2 	e_or2is r1,450
- 18000cc:	70 40 d1 81 	e_or2is r2,385
- 18000d0:	70 60 d1 81 	e_or2is r3,385
- 18000d4:	70 80 d1 ce 	e_or2is r4,462
- 18000d8:	70 a0 d1 80 	e_or2is r5,384
- 18000dc:	70 40 d1 81 	e_or2is r2,385
- 18000e0:	70 20 e1 c2 	e_lis   r1,450
- 18000e4:	70 40 e1 81 	e_lis   r2,385
- 18000e8:	70 60 e1 81 	e_lis   r3,385
- 18000ec:	70 80 e1 ce 	e_lis   r4,462
- 18000f0:	70 a0 e1 80 	e_lis   r5,384
- 18000f4:	70 40 e1 81 	e_lis   r2,385
- 18000f8:	70 20 e9 c2 	e_and2is. r1,450
- 18000fc:	70 40 e9 81 	e_and2is. r2,385
- 1800100:	70 60 e9 81 	e_and2is. r3,385
- 1800104:	70 80 e9 ce 	e_and2is. r4,462
- 1800108:	70 a0 e9 80 	e_and2is. r5,384
- 180010c:	70 40 e9 81 	e_and2is. r2,385
- 1800110:	70 01 99 c2 	e_cmp16i r1,450
- 1800114:	70 02 99 81 	e_cmp16i r2,385
- 1800118:	70 03 99 81 	e_cmp16i r3,385
- 180011c:	70 04 99 ce 	e_cmp16i r4,462
- 1800120:	70 05 99 80 	e_cmp16i r5,384
- 1800124:	70 02 99 81 	e_cmp16i r2,385
- 1800128:	70 01 a9 c2 	e_cmpl16i r1,450
- 180012c:	70 02 a9 81 	e_cmpl16i r2,385
- 1800130:	70 03 a9 81 	e_cmpl16i r3,385
- 1800134:	70 04 a9 ce 	e_cmpl16i r4,462
- 1800138:	70 05 a9 80 	e_cmpl16i r5,384
- 180013c:	70 02 a9 81 	e_cmpl16i r2,385
- 1800140:	70 01 b1 c2 	e_cmph16i r1,450
- 1800144:	70 02 b1 81 	e_cmph16i r2,385
- 1800148:	70 03 b1 81 	e_cmph16i r3,385
- 180014c:	70 04 b1 ce 	e_cmph16i r4,462
- 1800150:	70 05 b1 80 	e_cmph16i r5,384
- 1800154:	70 02 b1 81 	e_cmph16i r2,385
- 1800158:	70 01 b9 c2 	e_cmphl16i r1,450
- 180015c:	70 02 b9 81 	e_cmphl16i r2,385
- 1800160:	70 03 b9 81 	e_cmphl16i r3,385
- 1800164:	70 04 b9 ce 	e_cmphl16i r4,462
- 1800168:	70 05 b9 80 	e_cmphl16i r5,384
- 180016c:	70 02 b9 81 	e_cmphl16i r2,385
- 1800170:	70 01 89 c2 	e_add2i. r1,450
- 1800174:	70 02 89 81 	e_add2i. r2,385
- 1800178:	70 03 89 81 	e_add2i. r3,385
- 180017c:	70 04 89 ce 	e_add2i. r4,462
- 1800180:	70 05 89 80 	e_add2i. r5,384
- 1800184:	70 02 89 81 	e_add2i. r2,385
- 1800188:	70 01 91 c2 	e_add2is r1,450
- 180018c:	70 02 91 81 	e_add2is r2,385
- 1800190:	70 03 91 81 	e_add2is r3,385
- 1800194:	70 04 91 ce 	e_add2is r4,462
- 1800198:	70 05 91 80 	e_add2is r5,384
- 180019c:	70 02 91 81 	e_add2is r2,385
- 18001a0:	70 01 a1 c2 	e_mull2i r1,450
- 18001a4:	70 02 a1 81 	e_mull2i r2,385
- 18001a8:	70 03 a1 81 	e_mull2i r3,385
- 18001ac:	70 04 a1 ce 	e_mull2i r4,462
- 18001b0:	70 05 a1 80 	e_mull2i r5,384
- 18001b4:	70 02 a1 81 	e_mull2i r2,385
-018001b8 <sub3>:
- 18001b8:	00 04       	se_blr
-018001ba <sub4>:
- 18001ba:	00 04       	se_blr
-018001bc <sub5>:
- 18001bc:	00 04       	se_blr
+.* <sub1>:
+.*:	00 04       	se_blr
+.* <sub2>:
+.*:	00 04       	se_blr
+.* <vle_reloc_2>:
+.*:	70 20 c1 a2 	e_or2i  r1,418
+.*:	70 40 c1 81 	e_or2i  r2,385
+.*:	70 60 c1 81 	e_or2i  r3,385
+.*:	70 80 c1 ae 	e_or2i  r4,430
+.*:	70 a0 c1 80 	e_or2i  r5,384
+.*:	70 40 c1 81 	e_or2i  r2,385
+.*:	70 20 c9 a2 	e_and2i\. r1,418
+.*:	70 40 c9 81 	e_and2i\. r2,385
+.*:	70 60 c9 81 	e_and2i\. r3,385
+.*:	70 80 c9 ae 	e_and2i\. r4,430
+.*:	70 a0 c9 80 	e_and2i\. r5,384
+.*:	70 40 c9 81 	e_and2i\. r2,385
+.*:	70 20 d1 a2 	e_or2is r1,418
+.*:	70 40 d1 81 	e_or2is r2,385
+.*:	70 60 d1 81 	e_or2is r3,385
+.*:	70 80 d1 ae 	e_or2is r4,430
+.*:	70 a0 d1 80 	e_or2is r5,384
+.*:	70 40 d1 81 	e_or2is r2,385
+.*:	70 20 e1 a2 	e_lis   r1,418
+.*:	70 40 e1 81 	e_lis   r2,385
+.*:	70 60 e1 81 	e_lis   r3,385
+.*:	70 80 e1 ae 	e_lis   r4,430
+.*:	70 a0 e1 80 	e_lis   r5,384
+.*:	70 40 e1 81 	e_lis   r2,385
+.*:	70 20 e9 a2 	e_and2is\. r1,418
+.*:	70 40 e9 81 	e_and2is\. r2,385
+.*:	70 60 e9 81 	e_and2is\. r3,385
+.*:	70 80 e9 ae 	e_and2is\. r4,430
+.*:	70 a0 e9 80 	e_and2is\. r5,384
+.*:	70 40 e9 81 	e_and2is\. r2,385
+.*:	70 01 99 a2 	e_cmp16i r1,418
+.*:	70 02 99 81 	e_cmp16i r2,385
+.*:	70 03 99 81 	e_cmp16i r3,385
+.*:	70 04 99 ae 	e_cmp16i r4,430
+.*:	70 05 99 80 	e_cmp16i r5,384
+.*:	70 02 99 81 	e_cmp16i r2,385
+.*:	70 01 a9 a2 	e_cmpl16i r1,418
+.*:	70 02 a9 81 	e_cmpl16i r2,385
+.*:	70 03 a9 81 	e_cmpl16i r3,385
+.*:	70 04 a9 ae 	e_cmpl16i r4,430
+.*:	70 05 a9 80 	e_cmpl16i r5,384
+.*:	70 02 a9 81 	e_cmpl16i r2,385
+.*:	70 01 b1 a2 	e_cmph16i r1,418
+.*:	70 02 b1 81 	e_cmph16i r2,385
+.*:	70 03 b1 81 	e_cmph16i r3,385
+.*:	70 04 b1 ae 	e_cmph16i r4,430
+.*:	70 05 b1 80 	e_cmph16i r5,384
+.*:	70 02 b1 81 	e_cmph16i r2,385
+.*:	70 01 b9 a2 	e_cmphl16i r1,418
+.*:	70 02 b9 81 	e_cmphl16i r2,385
+.*:	70 03 b9 81 	e_cmphl16i r3,385
+.*:	70 04 b9 ae 	e_cmphl16i r4,430
+.*:	70 05 b9 80 	e_cmphl16i r5,384
+.*:	70 02 b9 81 	e_cmphl16i r2,385
+.*:	70 01 89 a2 	e_add2i\. r1,418
+.*:	70 02 89 81 	e_add2i\. r2,385
+.*:	70 03 89 81 	e_add2i\. r3,385
+.*:	70 04 89 ae 	e_add2i\. r4,430
+.*:	70 05 89 80 	e_add2i\. r5,384
+.*:	70 02 89 81 	e_add2i\. r2,385
+.*:	70 01 91 a2 	e_add2is r1,418
+.*:	70 02 91 81 	e_add2is r2,385
+.*:	70 03 91 81 	e_add2is r3,385
+.*:	70 04 91 ae 	e_add2is r4,430
+.*:	70 05 91 80 	e_add2is r5,384
+.*:	70 02 91 81 	e_add2is r2,385
+.*:	70 01 a1 a2 	e_mull2i r1,418
+.*:	70 02 a1 81 	e_mull2i r2,385
+.*:	70 03 a1 81 	e_mull2i r3,385
+.*:	70 04 a1 ae 	e_mull2i r4,430
+.*:	70 05 a1 80 	e_mull2i r5,384
+.*:	70 02 a1 81 	e_mull2i r2,385
+.* <sub3>:
+.*:	00 04       	se_blr
+.* <sub4>:
+.*:	00 04       	se_blr
+.* <sub5>:
+.*:	00 04       	se_blr