PPC64_OPT_LOCALENTRY is incompatible with tail calls

The save of r2 in __glink_PLTresolve is the culprit.  Remove it,
unless we know we need it for --plt-localentry.  --plt-localentry
should not be used with power10 pc-relative code that makes tail
calls.

The patch also removes use of r2 as a scratch reg in the ELFv2
__glink_PLTresolve.  Using r2 isn't a problem, this is just reducing
the number of scratch regs.

bfd/
	* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Depend on has_plt_localentry0.
	(LD_R0_0R11, ADD_R11_R0_R11): Define.
	(ppc64_elf_tls_setup): Disable params->plt_localentry0 when power10
	code detected.
	(ppc64_elf_size_stubs): Update __glink_PLTresolve eh_frame.
	(ppc64_elf_build_stubs): Move r2 save to start of __glink_PLTresolve,
	and only emit for has_plt_localentry0.  Don't use r2 in the stub.
ld/
	* testsuite/ld-powerpc/elfv2so.d,
	* testsuite/ld-powerpc/notoc2.d,
	* testsuite/ld-powerpc/tlsdesc.wf,
	* testsuite/ld-powerpc/tlsdesc2.d,
	* testsuite/ld-powerpc/tlsdesc2.wf,
	* testsuite/ld-powerpc/tlsopt5.d,
	* testsuite/ld-powerpc/tlsopt5.wf,
	* testsuite/ld-powerpc/tlsopt6.d,
	* testsuite/ld-powerpc/tlsopt6.wf: Update __glink_PLTresolve.

10 files changed, 45 insertions, 37 deletions

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 0662ac2..ea28290 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,15 @@
+2020-09-26  Alan Modra  <amodra@gmail.com>
+
+	* testsuite/ld-powerpc/elfv2so.d,
+	* testsuite/ld-powerpc/notoc2.d,
+	* testsuite/ld-powerpc/tlsdesc.wf,
+	* testsuite/ld-powerpc/tlsdesc2.d,
+	* testsuite/ld-powerpc/tlsdesc2.wf,
+	* testsuite/ld-powerpc/tlsopt5.d,
+	* testsuite/ld-powerpc/tlsopt5.wf,
+	* testsuite/ld-powerpc/tlsopt6.d,
+	* testsuite/ld-powerpc/tlsopt6.wf: Update __glink_PLTresolve.
+
 2020-09-24  Alan Modra  <amodra@gmail.com>
 
 	PR 26655
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 0162bd0..4018f05 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -74,12 +74,11 @@ Disassembly of section \.text:
 .*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
 .*:	(42 9f 00 05|05 00 9f 42) 	bcl     .*
 .*:	(7d 68 02 a6|a6 02 68 7d) 	mflr    r11
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(e8 4b ff f0|f0 ff 4b e8) 	ld      r2,-16\(r11\)
 .*:	(7c 08 03 a6|a6 03 08 7c) 	mtlr    r0
+.*:	(e8 0b ff f0|f0 ff 0b e8) 	ld      r0,-16\(r11\)
 .*:	(7d 8b 60 50|50 60 8b 7d) 	subf    r12,r11,r12
-.*:	(7d 62 5a 14|14 5a 62 7d) 	add     r11,r2,r11
-.*:	(38 0c ff d0|d0 ff 0c 38) 	addi    r0,r12,-48
+.*:	(7d 60 5a 14|14 5a 60 7d) 	add     r11,r0,r11
+.*:	(38 0c ff d4|d4 ff 0c 38) 	addi    r0,r12,-44
 .*:	(e9 8b 00 00|00 00 8b e9) 	ld      r12,0\(r11\)
 .*:	(78 00 f0 82|82 f0 00 78) 	rldicl  r0,r0,62,2
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
@@ -87,16 +86,16 @@ Disassembly of section \.text:
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 .* <f5@plt>:
-.*:	(4b ff ff c8|c8 ff ff 4b) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff cc|cc ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f3@plt>:
-.*:	(4b ff ff c4|c4 ff ff 4b) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff c8|c8 ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f2@plt>:
-.*:	(4b ff ff c0|c0 ff ff 4b) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff c4|c4 ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f4@plt>:
-.*:	(4b ff ff bc|bc ff ff 4b) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff c0|c0 ff ff 4b) 	b       .* <__glink_PLTresolve>
 
 .* <f1@plt>:
-.*:	(4b ff ff b8|b8 ff ff 4b) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff bc|bc ff ff 4b) 	b       .* <__glink_PLTresolve>
diff --git a/ld/testsuite/ld-powerpc/notoc2.d b/ld/testsuite/ld-powerpc/notoc2.d
index 1e519c0..3448f8b 100644
--- a/ld/testsuite/ld-powerpc/notoc2.d
+++ b/ld/testsuite/ld-powerpc/notoc2.d
@@ -22,8 +22,8 @@ Disassembly of section \.text:
 .*:	(39 80 ff ff|ff ff 80 39) 
 .*:	(06 10 00 00|00 00 10 06) 	pla     r12,0
 .*:	(39 80 00 00|00 00 80 39) 
-.*:	(06 10 00 00|00 00 10 06) 	pla     r3,92
-.*:	(38 60 00 5c|5c 00 60 38) 
+.*:	(06 10 00 00|00 00 10 06) 	pla     r3,88
+.*:	(38 60 00 58|58 00 60 38) 
 .*:	(4b ff ff 99|99 ff ff 4b) 	bl      .* <.*\.plt_call\.puts>
 .*:	(60 00 00 00|00 00 00 60) 	nop
 #pass
diff --git a/ld/testsuite/ld-powerpc/tlsdesc.wf b/ld/testsuite/ld-powerpc/tlsdesc.wf
index 09503fa..e7d4522 100644
--- a/ld/testsuite/ld-powerpc/tlsdesc.wf
+++ b/ld/testsuite/ld-powerpc/tlsdesc.wf
@@ -38,9 +38,9 @@ Contents of the \.eh_frame section:
   DW_CFA_nop
 
 0+4c 0+14 0+50 FDE cie=0+ pc=0+2f8\.\.0+32c
-  DW_CFA_advance_loc: 4 to 0+2fc
+  DW_CFA_advance_loc: 8 to 0+300
   DW_CFA_register: r65 in r12
-  DW_CFA_advance_loc: 20 to 0+310
+  DW_CFA_advance_loc: 16 to 0+310
   DW_CFA_restore_extended: r65
 
 0+64 0+10 0+68 FDE cie=0+ pc=0+2e0\.\.0+2ec
diff --git a/ld/testsuite/ld-powerpc/tlsdesc2.d b/ld/testsuite/ld-powerpc/tlsdesc2.d
index 47aedbe..c271c94 100644
--- a/ld/testsuite/ld-powerpc/tlsdesc2.d
+++ b/ld/testsuite/ld-powerpc/tlsdesc2.d
@@ -53,12 +53,11 @@ Disassembly of section \.text:
 .*:	(7c 08 02 a6|a6 02 08 7c) 	mflr    r0
 .*:	(42 9f 00 05|05 00 9f 42) 	bcl     .*
 .*:	(7d 68 02 a6|a6 02 68 7d) 	mflr    r11
-.*:	(f8 41 00 18|18 00 41 f8) 	std     r2,24\(r1\)
-.*:	(e8 4b ff f0|f0 ff 4b e8) 	ld      r2,-16\(r11\)
 .*:	(7c 08 03 a6|a6 03 08 7c) 	mtlr    r0
+.*:	(e8 0b ff f0|f0 ff 0b e8) 	ld      r0,-16\(r11\)
 .*:	(7d 8b 60 50|50 60 8b 7d) 	subf    r12,r11,r12
-.*:	(7d 62 5a 14|14 5a 62 7d) 	add     r11,r2,r11
-.*:	(38 0c ff d0|d0 ff 0c 38) 	addi    r0,r12,-48
+.*:	(7d 60 5a 14|14 5a 60 7d) 	add     r11,r0,r11
+.*:	(38 0c ff d4|d4 ff 0c 38) 	addi    r0,r12,-44
 .*:	(e9 8b 00 00|00 00 8b e9) 	ld      r12,0\(r11\)
 .*:	(78 00 f0 82|82 f0 00 78) 	rldicl  r0,r0,62,2
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
@@ -66,4 +65,4 @@ Disassembly of section \.text:
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 
 .* <__tls_get_addr_opt@plt>:
-.*:	(4b ff ff c8|c8 ff ff 4b) 	b       .* <__glink_PLTresolve>
+.*:	(4b ff ff cc|cc ff ff 4b) 	b       .* <__glink_PLTresolve>
diff --git a/ld/testsuite/ld-powerpc/tlsdesc2.wf b/ld/testsuite/ld-powerpc/tlsdesc2.wf
index cb92c29..79a417b 100644
--- a/ld/testsuite/ld-powerpc/tlsdesc2.wf
+++ b/ld/testsuite/ld-powerpc/tlsdesc2.wf
@@ -37,10 +37,10 @@ Contents of the \.eh_frame section:
   DW_CFA_nop
   DW_CFA_nop
 
-0+4c 0+14 0+50 FDE cie=0+ pc=0+318\.\.0+354
-  DW_CFA_advance_loc: 4 to 0+31c
+0+4c 0+14 0+50 FDE cie=0+ pc=0+318\.\.0+350
+  DW_CFA_advance_loc: 8 to 0+320
   DW_CFA_register: r65 in r0
-  DW_CFA_advance_loc: 28 to 0+338
+  DW_CFA_advance_loc: 8 to 0+328
   DW_CFA_restore_extended: r65
 
 0+64 0+10 0+68 FDE cie=0+ pc=0+300\.\.0+30c
diff --git a/ld/testsuite/ld-powerpc/tlsopt5.d b/ld/testsuite/ld-powerpc/tlsopt5.d
index 0fcb798..efd6deb 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5.d
+++ b/ld/testsuite/ld-powerpc/tlsopt5.d
@@ -49,12 +49,11 @@ Disassembly of section \.text:
 .*:	(a6 02 08 7c|7c 08 02 a6) 	mflr    r0
 .*:	(05 00 9f 42|42 9f 00 05) 	bcl     .*
 .*:	(a6 02 68 7d|7d 68 02 a6) 	mflr    r11
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(f0 ff 4b e8|e8 4b ff f0) 	ld      r2,-16\(r11\)
 .*:	(a6 03 08 7c|7c 08 03 a6) 	mtlr    r0
+.*:	(f0 ff 0b e8|e8 0b ff f0) 	ld      r0,-16\(r11\)
 .*:	(50 60 8b 7d|7d 8b 60 50) 	subf    r12,r11,r12
-.*:	(14 5a 62 7d|7d 62 5a 14) 	add     r11,r2,r11
-.*:	(d0 ff 0c 38|38 0c ff d0) 	addi    r0,r12,-48
+.*:	(14 5a 60 7d|7d 60 5a 14) 	add     r11,r0,r11
+.*:	(d4 ff 0c 38|38 0c ff d4) 	addi    r0,r12,-44
 .*:	(00 00 8b e9|e9 8b 00 00) 	ld      r12,0\(r11\)
 .*:	(82 f0 00 78|78 00 f0 82) 	rldicl  r0,r0,62,2
 .*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
@@ -62,7 +61,7 @@ Disassembly of section \.text:
 .*:	(20 04 80 4e|4e 80 04 20) 	bctr
 
 .* <__tls_get_addr_opt@plt>:
-.*	(c8 ff ff 4b|4b ff ff c8) 	b       .*
+.*	(cc ff ff 4b|4b ff ff cc) 	b       .*
 
 .* <aaaaa@plt>:
-.*:	(c4 ff ff 4b|4b ff ff c4) 	b       .*
+.*:	(c8 ff ff 4b|4b ff ff c8) 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsopt5.wf b/ld/testsuite/ld-powerpc/tlsopt5.wf
index f045361..84bd94e 100644
--- a/ld/testsuite/ld-powerpc/tlsopt5.wf
+++ b/ld/testsuite/ld-powerpc/tlsopt5.wf
@@ -16,9 +16,9 @@ Contents of the \.eh_frame section:
   DW_CFA_restore_extended: r65
 
 0+2c 0+14 0+30 FDE cie=0+ pc=.*
-  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_advance_loc: 8 to .*
   DW_CFA_register: r65 in r0
-  DW_CFA_advance_loc: 28 to .*
+  DW_CFA_advance_loc: 8 to .*
   DW_CFA_restore_extended: r65
 
 0+44 0+10 0+48 FDE cie=0+ pc=.*
diff --git a/ld/testsuite/ld-powerpc/tlsopt6.d b/ld/testsuite/ld-powerpc/tlsopt6.d
index 4ca6409..15def71 100644
--- a/ld/testsuite/ld-powerpc/tlsopt6.d
+++ b/ld/testsuite/ld-powerpc/tlsopt6.d
@@ -67,12 +67,11 @@ Disassembly of section \.text:
 .*:	(a6 02 08 7c|7c 08 02 a6) 	mflr    r0
 .*:	(05 00 9f 42|42 9f 00 05) 	bcl     .*
 .*:	(a6 02 68 7d|7d 68 02 a6) 	mflr    r11
-.*:	(18 00 41 f8|f8 41 00 18) 	std     r2,24\(r1\)
-.*:	(f0 ff 4b e8|e8 4b ff f0) 	ld      r2,-16\(r11\)
 .*:	(a6 03 08 7c|7c 08 03 a6) 	mtlr    r0
+.*:	(f0 ff 0b e8|e8 0b ff f0) 	ld      r0,-16\(r11\)
 .*:	(50 60 8b 7d|7d 8b 60 50) 	subf    r12,r11,r12
-.*:	(14 5a 62 7d|7d 62 5a 14) 	add     r11,r2,r11
-.*:	(d0 ff 0c 38|38 0c ff d0) 	addi    r0,r12,-48
+.*:	(14 5a 60 7d|7d 60 5a 14) 	add     r11,r0,r11
+.*:	(d4 ff 0c 38|38 0c ff d4) 	addi    r0,r12,-44
 .*:	(00 00 8b e9|e9 8b 00 00) 	ld      r12,0\(r11\)
 .*:	(82 f0 00 78|78 00 f0 82) 	rldicl  r0,r0,62,2
 .*:	(a6 03 89 7d|7d 89 03 a6) 	mtctr   r12
@@ -80,7 +79,7 @@ Disassembly of section \.text:
 .*:	(20 04 80 4e|4e 80 04 20) 	bctr
 
 .* <__tls_get_addr_opt@plt>:
-.*	(c8 ff ff 4b|4b ff ff c8) 	b       .*
+.*	(cc ff ff 4b|4b ff ff cc) 	b       .*
 
 .* <aaaaa@plt>:
-.*:	(c4 ff ff 4b|4b ff ff c4) 	b       .*
+.*:	(c8 ff ff 4b|4b ff ff c8) 	b       .*
diff --git a/ld/testsuite/ld-powerpc/tlsopt6.wf b/ld/testsuite/ld-powerpc/tlsopt6.wf
index abb414a..c2b9616 100644
--- a/ld/testsuite/ld-powerpc/tlsopt6.wf
+++ b/ld/testsuite/ld-powerpc/tlsopt6.wf
@@ -38,9 +38,9 @@ Contents of the \.eh_frame section:
   DW_CFA_nop
 
 0+4c 0+14 0+50 FDE cie=0+ pc=.*
-  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_advance_loc: 8 to .*
   DW_CFA_register: r65 in r0
-  DW_CFA_advance_loc: 28 to .*
+  DW_CFA_advance_loc: 8 to .*
   DW_CFA_restore_extended: r65
 
 0+64 0+10 0+68 FDE cie=0+ pc=.*