RISC-V: Add support for XCvBitmanip extension in CV32E40PHEADmaster

Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:
	* elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip`
	instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:
	* config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/march-help.l: Add xcvbitmanip.
	* testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip.d: New Test.
	* testsuite/gas/riscv/x-cv-bitmanip.s: New Test.

include/opcode/ChangeLog:
	* riscv-opc.h: Add corresponding MATCH and MASK macros for
	XCVbitmanip.
	* riscv.h: Add corresponding EXTRACT and ENCODE macros for
	XCVbitmanip.
	(enum riscv_insn_class): Add the XCVbitmanip instruction class.

opcodes/ChangeLog:
	* riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`.
	* riscv-opc.c: Add XCvBitmanip instructions.

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