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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 11:27:23 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-06-25 13:38:48 +0100 |
| commit | f5f38efc0a20cb50105da4fd2f656cda4561ccc2 (patch) | |
| tree | cb938e82dc5a9326ba5d7c15b593eba902e7f2e8 /include | |
| parent | 8e018c070ce41fe83f09b4fde8c2b2d9ad473e25 (diff) | |
| download | binutils-f5f38efc0a20cb50105da4fd2f656cda4561ccc2.zip binutils-f5f38efc0a20cb50105da4fd2f656cda4561ccc2.tar.gz binutils-f5f38efc0a20cb50105da4fd2f656cda4561ccc2.tar.bz2 | |
aarch64: Fix sve2p1 dupq instruction operands.
This patch fixes the syntax of sve2p1 "dupq" instruction by modifying the way
2nd operand does the encoding and decoding using the [<imm>] value.
dupq makes use of already existing aarch64_ins_sve_index and aarch64_ext_sve_index
inserter and extractor functions. The definitions of aarch64_ins_sve_index_imm (inserter)
and aarch64_ext_sve_index_imm (extractor) is removed in this patch.
This issues was reported here:
https://sourceware.org/pipermail/binutils/2024-February/132408.html
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 3410a76..78f19b6 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -786,8 +786,8 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ - AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ + AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */ AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ |