diff options
| author | Nelson Chu <nelson.chu@sifive.com> | 2024-11-20 16:30:39 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-11-22 09:56:54 +0800 |
| commit | 595e49a4b7c6769ef23a2573148db72872c61935 (patch) | |
| tree | 4cb033daf7e71ae46317ed497db4e9260fe66d93 /include | |
| parent | 87480dcfb62faa25b9fc6e46ae58a090ac2e43dc (diff) | |
| download | binutils-595e49a4b7c6769ef23a2573148db72872c61935.zip binutils-595e49a4b7c6769ef23a2573148db72872c61935.tar.gz binutils-595e49a4b7c6769ef23a2573148db72872c61935.tar.bz2 | |
RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf
Those SiFive extensions have been published on the web for a while, and we plan
to implement intrinsics in GCC for those instructions soon.
NOTE: The original patch was written by Nelson when he was still working at
SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson
with his SiFive email.
Document links:
xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification
xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 22 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 3 |
2 files changed, 25 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8165686..253148b 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3745,6 +3745,28 @@ /* Vendor-specific (SiFive) cease instruction. */ #define MATCH_SF_CEASE 0x30500073 #define MASK_SF_CEASE 0xffffffff +/* SiFive custom int8 matrix-multiply instruction. */ +#define MATCH_SFVQMACCU4X8X4 0xf200205b +#define MASK_SFVQMACCU4X8X4 0xfe00707f +#define MATCH_SFVQMACC4X8X4 0xf600205b +#define MASK_SFVQMACC4X8X4 0xfe00707f +#define MATCH_SFVQMACCUS4X8X4 0xfa00205b +#define MASK_SFVQMACCUS4X8X4 0xfe00707f +#define MATCH_SFVQMACCSU4X8X4 0xfe00205b +#define MASK_SFVQMACCSU4X8X4 0xfe00707f +#define MATCH_SFVQMACCU2X8X2 0xb200205b +#define MASK_SFVQMACCU2X8X2 0xfe00707f +#define MATCH_SFVQMACC2X8X2 0xb600205b +#define MASK_SFVQMACC2X8X2 0xfe00707f +#define MATCH_SFVQMACCUS2X8X2 0xba00205b +#define MASK_SFVQMACCUS2X8X2 0xfe00707f +#define MATCH_SFVQMACCSU2X8X2 0xbe00205b +#define MASK_SFVQMACCSU2X8X2 0xfe00707f +/* FP32-to-int8 Ranged Clip Instructions (Xsfvfnrclipxfqf). */ +#define MATCH_SFVFNRCLIPXUFQF 0x8a00505b +#define MASK_SFVFNRCLIPXUFQF 0xfe00707f +#define MATCH_SFVFNRCLIPXFQF 0x8e00505b +#define MASK_SFVFNRCLIPXFQF 0xfe00707f /* Unprivileged Counter/Timers CSR addresses. */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 5e5131e..fedfdd2 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -554,6 +554,9 @@ enum riscv_insn_class INSN_CLASS_XVENTANACONDOPS, INSN_CLASS_XSFVCP, INSN_CLASS_XSFCEASE, + INSN_CLASS_XSFVQMACCQOQ, + INSN_CLASS_XSFVQMACCDOD, + INSN_CLASS_XSFVFNRCLIPXFQF, }; /* This structure holds information for a particular instruction. */ |