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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2023-11-16 14:27:25 +0000 |
|---|---|---|
| committer | srinath <srinath.parvathaneni@arm.com> | 2023-11-16 14:29:30 +0000 |
| commit | 44167ca8da9aada2e574525e0548347f80442b09 (patch) | |
| tree | 91be08040fca57f4052e70a0649e38b718947549 /include | |
| parent | 281fda33bcf47d5d541e28aac1e5772ebdf1eb1a (diff) | |
| download | binutils-44167ca8da9aada2e574525e0548347f80442b09.zip binutils-44167ca8da9aada2e574525e0548347f80442b09.tar.gz binutils-44167ca8da9aada2e574525e0548347f80442b09.tar.bz2 | |
aarch64: Add support for VMSA feature enhancements.
This patch adds the permission model enhancement and memory
attribute index enhancement features and their corresponding
system registers in AArch64 assembler.
Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
Memory Attribute Index Enhancement (FEAT_AIE)
Extension to Translation Control Registers (FEAT_TCR2)
These features are available by default from Armv9.4-A architecture.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 792d6a4..6323383 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -185,6 +185,18 @@ enum aarch64_feature_bit { AARCH64_FEATURE_PFAR, /* Address Translate Stage 1. */ AARCH64_FEATURE_ATS1A, + /* Memory Attribute Index Enhancement. */ + AARCH64_FEATURE_AIE, + /* Stage 1 Permission Indirection Extension. */ + AARCH64_FEATURE_S1PIE, + /* Stage 2 Permission Indirection Extension. */ + AARCH64_FEATURE_S2PIE, + /* Stage 1 Permission Overlay Extension. */ + AARCH64_FEATURE_S1POE, + /* Stage 2 Permission Overlay Extension. */ + AARCH64_FEATURE_S2POE, + /* Extension to Translation Control Registers. */ + AARCH64_FEATURE_TCR2, AARCH64_NUM_FEATURES }; @@ -248,7 +260,14 @@ enum aarch64_feature_bit { | AARCH64_FEATBIT (X, SCTLR2) \ | AARCH64_FEATBIT (X, FGT2) \ | AARCH64_FEATBIT (X, PFAR) \ - | AARCH64_FEATBIT (X, ATS1A)) + | AARCH64_FEATBIT (X, ATS1A) \ + | AARCH64_FEATBIT (X, AIE) \ + | AARCH64_FEATBIT (X, S1PIE) \ + | AARCH64_FEATBIT (X, S2PIE) \ + | AARCH64_FEATBIT (X, S1POE) \ + | AARCH64_FEATBIT (X, S2POE) \ + | AARCH64_FEATBIT (X, TCR2) \ + ) #define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \ | AARCH64_FEATBIT (X, F16) \ |