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| author | Jim Wilson <jimw@sifive.com> | 2018-08-30 13:23:12 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2018-08-30 13:23:12 -0700 |
| commit | 43135d3b15ce10a786704f9bb4736d834d6581a8 (patch) | |
| tree | 09a46598dd29db01cd479dfc5f23f29abf68f8cb /include | |
| parent | a869991180094d4cbeb0bd2f275fc7b30e513fb7 (diff) | |
| download | binutils-43135d3b15ce10a786704f9bb4736d834d6581a8.zip binutils-43135d3b15ce10a786704f9bb4736d834d6581a8.tar.gz binutils-43135d3b15ce10a786704f9bb4736d834d6581a8.tar.bz2 | |
RISC-V: Allow instruction require more than one extension
2018-08-29 Kito Cheng <kito@andestech.com>
gas/
* config/tc-riscv.c (riscv_subset_supports): New argument:
xlen_required.
(riscv_multi_subset_supports): New function, able to check more
than one extension.
(riscv_ip): Use riscv_multi_subset_supports instead of
riscv_subset_supports.
(riscv_set_arch): Update call-site for riscv_subset_supports.
(riscv_after_parse_args): Likewise.
include/
*opcode/riscv.h (MAX_SUBSET_NUM): New.
(riscv_opcode): Add xlen_requirement field and change type of
subset.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Check XLEN by
riscv_opcode.xlen_requirement.
* riscv-opc.c (riscv_opcodes): Update for struct change.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 6c19b1d..b8fcefd 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2018-08-30 Kito Cheng <kito@andestech.com> + + * opcode/riscv.h (MAX_SUBSET_NUM): New. + (riscv_opcode): Add xlen_requirement field and change type of + subset. + 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d9a5438..68047a5 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -281,14 +281,20 @@ static const char * const riscv_pred_succ[16] = #define EXTRACT_OPERAND(FIELD, INSN) \ EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) +/* The maximal number of subset can be required. */ +#define MAX_SUBSET_NUM 4 + /* This structure holds information for a particular instruction. */ struct riscv_opcode { /* The name of the instruction. */ const char *name; - /* The ISA subset name (I, M, A, F, D, Xextension). */ - const char *subset; + /* The requirement of xlen for the instruction, 0 if no requirement. */ + int xlen_requirement; + /* An array of ISA subset name (I, M, A, F, D, Xextension), must ended + with a NULL pointer sential. */ + const char *subset[MAX_SUBSET_NUM]; /* A string describing the arguments for this instruction. */ const char *args; /* The basic opcode for the instruction. When assembling, this |