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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-06-30 22:43:50 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:40 -0600 |
| commit | fce8fef965904dc16ffba2388ba44003e61cd908 (patch) | |
| tree | 4317bc3c28796b7ba77af3a5a585380ad8c90318 /include/opcode/riscv.h | |
| parent | 9d469329d229da8e2a6d7b70a2be3988aa45a277 (diff) | |
| download | binutils-fce8fef965904dc16ffba2388ba44003e61cd908.zip binutils-fce8fef965904dc16ffba2388ba44003e61cd908.tar.gz binutils-fce8fef965904dc16ffba2388ba44003e61cd908.tar.bz2 | |
RISC-V: Add support for the Zvkned ISA extension
Zvkned is part of the vector crypto extensions.
This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvkned.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvkned.d: New test.
* testsuite/gas/riscv/zvkned.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VAESDF_VS): New.
(MASK_VAESDF_VS): New.
(MATCH_VAESDF_VV): New.
(MASK_VAESDF_VV): New.
(MATCH_VAESDM_VS): New.
(MASK_VAESDM_VS): New.
(MATCH_VAESDM_VV): New.
(MASK_VAESDM_VV): New.
(MATCH_VAESEF_VS): New.
(MASK_VAESEF_VS): New.
(MATCH_VAESEF_VV): New.
(MASK_VAESEF_VV): New.
(MATCH_VAESEM_VS): New.
(MASK_VAESEM_VS): New.
(MATCH_VAESEM_VV): New.
(MASK_VAESEM_VV): New.
(MATCH_VAESKF1_VI): New.
(MASK_VAESKF1_VI): New.
(MATCH_VAESKF2_VI): New.
(MASK_VAESKF2_VI): New.
(MATCH_VAESZ_VS): New.
(MASK_VAESZ_VS): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvkned.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvkned instructions.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index b209886..5d55dbc 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -417,6 +417,7 @@ enum riscv_insn_class INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, INSN_CLASS_ZVKG, + INSN_CLASS_ZVKNED, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, |