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| author | Jin Ma <jinma@linux.alibaba.com> | 2025-03-17 14:07:35 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-03-18 12:27:26 +0800 |
| commit | 66b81b40dcf1fe5739c6c8138b242e47ebab0c8a (patch) | |
| tree | b86d4fd2f21e213b095eecf596637b7b47dc6234 /include/opcode/riscv.h | |
| parent | e4c9f0e6c3a665c0a711dc6bf74e37dfc370e28c (diff) | |
| download | binutils-66b81b40dcf1fe5739c6c8138b242e47ebab0c8a.zip binutils-66b81b40dcf1fe5739c6c8138b242e47ebab0c8a.tar.gz binutils-66b81b40dcf1fe5739c6c8138b242e47ebab0c8a.tar.bz2 | |
RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds the additional extension "XTheadVdot" based on the
"V" extension, and it provides four 8-bit multiply and add with
32-bit instructions for the "v" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([2]).
Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com>
[1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot
[2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support
for "XTheadVdot" extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi: Likewise.
* testsuite/gas/riscv/march-help.l: Likewise.
* testsuite/gas/riscv/x-thead-vdot.d: New test.
* testsuite/gas/riscv/x-thead-vdot.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New.
* opcode/riscv.h (enum riscv_insn_class): Add insn class for
XTheadVdot.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6bcea63..1f4bede 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -554,6 +554,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADVECTOR, + INSN_CLASS_XTHEADVDOT, INSN_CLASS_XTHEADZVAMO, INSN_CLASS_XVENTANACONDOPS, INSN_CLASS_XSFVCP, |