RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.

Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the
spec versions stuff to bfd/cpu-riscv.h.  Also move the csr stuff and
ext_version_table to gas/config/tc-riscv.c for internal use.  To avoid
too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS
macros.  Therefore, assembler/dis-assembler/linker/gdb can get all spec
versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff
are defined there uniformly.

bfd/
    * Makefile.am: Added cpu-riscv.h.
    * Makefile.in: Regenerated.
    * po/SRC-POTFILES.in: Regenerated.
    * cpu-riscv.h: Added to support spec versions controlling.
    Also added extern arrays and functions for cpu-riscv.c.
    (enum riscv_spec_class): Define all spec classes here uniformly.
    (struct riscv_spec): Added for all specs.
    (RISCV_GET_SPEC_CLASS): Added to reduce repeated code.
    (RISCV_GET_SPEC_NAME): Likewise.
    (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class.
    (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class.
    (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name.
    * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec.
    (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS.
    (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME.
    (riscv_priv_specs): Moved below.
    (riscv_get_priv_spec_class_from_numbers): Likewise, updated.
    (riscv_isa_specs): Moved from include/opcode/riscv.h.
    * elfnn-riscv.c: Included cpu-riscv.h.
    (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec.
    * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h.
    (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h.
    * elfxx-riscv.h: Removed extern functions to cpu-riscv.h.
gas/
    * config/tc-riscv.c: Included cpu-riscv.h.
    (enum riscv_csr_clas): Moved from include/opcode/riscv.h.
    (struct riscv_csr_extra): Likewise.
    (struct riscv_ext_version): Likewise.
    (ext_version_table): Moved from opcodes/riscv-opc.c.
    (default_isa_spec): Updated type to riscv_spec_class.
    (default_priv_spec): Likewise.
    (riscv_set_default_isa_spec): Updated.
    (init_ext_version_hash): Likewise.
    (riscv_init_csr_hash): Likewise, also fixed indent.
include/
    * opcode/riscv.h: Moved stuff and make the file tidy.
opcodes/
    * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
    (default_priv_spec): Updated type to riscv_spec_class.
    (parse_riscv_dis_option): Updated.
    * riscv-opc.c: Moved stuff and make the file tidy.

1 files changed, 4 insertions, 0 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index 6c3a835..0f4936e 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
+
+	* opcode/riscv.h: Moved stuff and make the file tidy.
+
 2021-02-15  Andreas Krebbel  <krebbel@linux.ibm.com>
 
 	* opcode/s390.h (enum s390_opcode_cpu_val): Add