ChangeLog rotation

1 files changed, 890 insertions, 0 deletions

diff --git a/include/ChangeLog-2018 b/include/ChangeLog-2018
new file mode 100644
index 0000000..53c423b
--- /dev/null
+++ b/include/ChangeLog-2018
@@ -0,0 +1,890 @@
+2018-12-28  Alan Modra  <amodra@gmail.com>
+
+	PR 24028
+	* opcode/ppc.h (PPC_INT_FMT): Delete.
+
+2018-12-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/23900
+	* elf/common.h (PT_GNU_PROPERTY): New.
+	(GNU_PROPERTY_X86_UINT32_VALID): Removed.
+
+2018-12-11  Nick Clifton  <nickc@redhat.com>
+
+	PR 88409
+	* demangle.h (DEMANGLE_RECURSION_LIMIT): Increase to 2048.
+
+2018-12-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* bfdlink.h (bfd_link_info): Add has_map_file.
+
+2018-12-07  Nick Clifton  <nickc@redhat.com>
+
+	* demangle.h (DMGL_NO_RECURSE_LIMIT): Define.
+        (DEMANGLE_RECURSION_LIMIT): Define
+
+2018-12-06  Alan Modra  <amodra@gmail.com>
+
+	* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
+
+2018-12-06  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* dis-asm.h (riscv_symbol_is_valid): Declare.
+	* opcode/riscv.h (RISCV_FAKE_LABEL_NAME): Define.
+	(RISCV_FAKE_LABEL_CHAR): Define.
+
+2018-12-03  Kito Cheng  <kito@andestech.com>
+
+	* opcode/riscv.h (riscv_opcode): Change type of xlen_requirement to
+	unsigned.
+
+2018-11-27  Jim Wilson  <jimw@sifive.com>
+
+	* opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New.
+	(OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New.
+
+2018-11-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* opcode/arm.h (ARM_AEXT_V6M_ONLY): Merge into its use in ARM_AEXT_V6M.
+	(ARM_ARCH_V6M_ONLY): Remove.
+	(ARM_EXT_V1, ARM_EXT_V2, ARM_EXT_V2S, ARM_EXT_V3, ARM_EXT_V3M,
+	ARM_EXT_V4, ARM_EXT_V4T, ARM_EXT_V5, ARM_EXT_V5T, ARM_EXT_V5ExP,
+	ARM_EXT_V5E, ARM_EXT_V5J, ARM_EXT_V6, ARM_EXT_V6K, ARM_EXT_V8,
+	ARM_EXT_V6T2, ARM_EXT_DIV, ARM_EXT_V5E_NOTM, ARM_EXT_V6_NOTM,
+	ARM_EXT_V7, ARM_EXT_V7A, ARM_EXT_V7R, ARM_EXT_V7M, ARM_EXT_V6M,
+	ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR, ARM_EXT_V6_DSP, ARM_EXT_MP,
+	ARM_EXT_SEC, ARM_EXT_OS, ARM_EXT_ADIV, ARM_EXT_VIRT, ARM_EXT2_PAN,
+	ARM_EXT2_V8_2A, ARM_EXT2_V8M, ARM_EXT2_ATOMICS, ARM_EXT2_V6T2_V8M,
+	ARM_EXT2_FP16_INST, ARM_EXT2_V8M_MAIN, ARM_EXT2_RAS, ARM_EXT2_V8_3A,
+	ARM_EXT2_V8A, ARM_EXT2_V8_4A, ARM_EXT2_FP16_FML, ARM_EXT2_V8_5A,
+	ARM_EXT2_SB, ARM_EXT2_PREDRES, ARM_CEXT_XSCALE, ARM_CEXT_MAVERICK,
+	ARM_CEXT_IWMMXT, ARM_CEXT_IWMMXT2, FPU_ENDIAN_PURE, FPU_ENDIAN_BIG,
+	FPU_FPA_EXT_V1, FPU_FPA_EXT_V2, FPU_MAVERICK, FPU_VFP_EXT_V1xD,
+	FPU_VFP_EXT_V1, FPU_VFP_EXT_V2, FPU_VFP_EXT_V3xD, FPU_VFP_EXT_V3,
+	FPU_NEON_EXT_V1, FPU_VFP_EXT_D32, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
+	FPU_VFP_EXT_FMA, FPU_VFP_EXT_ARMV8, FPU_NEON_EXT_ARMV8,
+	FPU_CRYPTO_EXT_ARMV8, CRC_EXT_ARMV8, FPU_VFP_EXT_ARMV8xD,
+	FPU_NEON_EXT_RDMA, FPU_NEON_EXT_DOTPROD, ARM_AEXT_V1, ARM_AEXT_V2,
+	ARM_AEXT_V2S, ARM_AEXT_V3, ARM_AEXT_V3M, ARM_AEXT_V4xM, ARM_AEXT_V4,
+	ARM_AEXT_V4TxM, ARM_AEXT_V4T, ARM_AEXT_V5xM, ARM_AEXT_V5,
+	ARM_AEXT_V5TxM, ARM_AEXT_V5T, ARM_AEXT_V5TExP, ARM_AEXT_V5TE,
+	ARM_AEXT_V5TEJ, ARM_AEXT_V6, ARM_AEXT_V6K, ARM_AEXT_V6Z, ARM_AEXT_V6KZ,
+	ARM_AEXT_V6T2, ARM_AEXT_V6KT2, ARM_AEXT_V6ZT2, ARM_AEXT_V6KZT2,
+	ARM_AEXT_V7_ARM, ARM_AEXT_V7A, ARM_AEXT_V7VE, ARM_AEXT_V7R,
+	ARM_AEXT_NOTM, ARM_AEXT_V6M_ONLY, ARM_AEXT_V6M, ARM_AEXT_V6SM,
+	ARM_AEXT_V7M, ARM_AEXT_V7, ARM_AEXT_V7EM, ARM_AEXT_V8A, ARM_AEXT2_V8A,
+	ARM_AEXT2_V8_1A, ARM_AEXT2_V8_2A, ARM_AEXT2_V8_3A, ARM_AEXT2_V8_4A,
+	ARM_AEXT2_V8_5A, ARM_AEXT_V8M_BASE, ARM_AEXT_V8M_MAIN,
+	ARM_AEXT_V8M_MAIN_DSP, ARM_AEXT2_V8M, ARM_AEXT2_V8M_BASE,
+	ARM_AEXT2_V8M_MAIN, ARM_AEXT2_V8M_MAIN_DSP, ARM_AEXT_V8R,
+	ARM_AEXT2_V8R, FPU_VFP_V1xD, FPU_VFP_V1, FPU_VFP_V2, FPU_VFP_V3D16,
+	FPU_VFP_V3, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4, FPU_VFP_V4_SP_D16,
+	FPU_VFP_V5D16, FPU_VFP_ARMV8, FPU_NEON_ARMV8, FPU_CRYPTO_ARMV8,
+	FPU_VFP_HARD, FPU_FPA, FPU_ARCH_VFP, FPU_ARCH_FPE, FPU_ARCH_FPA,
+	FPU_ARCH_VFP_V1xD, FPU_ARCH_VFP_V1, FPU_ARCH_VFP_V2,
+	FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_FP16,
+	FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_NEON_V1, FPU_ARCH_VFP_V3_PLUS_NEON_V1,
+	FPU_ARCH_NEON_FP16, FPU_ARCH_VFP_HARD, FPU_ARCH_VFP_V4,
+	FPU_ARCH_VFP_V4D16, FPU_ARCH_VFP_V4_SP_D16, FPU_ARCH_VFP_V5D16,
+	FPU_ARCH_VFP_V5_SP_D16, FPU_ARCH_NEON_VFP_V4, FPU_ARCH_VFP_ARMV8,
+	FPU_ARCH_NEON_VFP_ARMV8, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+	FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD, ARCH_CRC_ARMV8,
+	FPU_ARCH_NEON_VFP_ARMV8_1, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
+	FPU_ARCH_DOTPROD_NEON_VFP_ARMV8, ARM_ARCH_V1, ARM_ARCH_V2,
+	ARM_ARCH_V2S, ARM_ARCH_V3, ARM_ARCH_V3M, ARM_ARCH_V4xM, ARM_ARCH_V4,
+	ARM_ARCH_V4TxM, ARM_ARCH_V4T, ARM_ARCH_V5xM, ARM_ARCH_V5,
+	ARM_ARCH_V5TxM, ARM_ARCH_V5T, ARM_ARCH_V5TExP, ARM_ARCH_V5TE,
+	ARM_ARCH_V5TEJ, ARM_ARCH_V6, ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6KZ,
+	ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, ARM_ARCH_V6KZT2,
+	ARM_ARCH_V6M, ARM_ARCH_V6SM, ARM_ARCH_V7, ARM_ARCH_V7A, ARM_ARCH_V7VE,
+	ARM_ARCH_V7R, ARM_ARCH_V7M, ARM_ARCH_V7EM, ARM_ARCH_V8A,
+	ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A, ARM_ARCH_V8_3A,
+	ARM_ARCH_V8_4A, ARM_ARCH_V8_5A, ARM_ARCH_V8M_BASE, ARM_ARCH_V8M_MAIN,
+	ARM_ARCH_V8M_MAIN_DSP, ARM_ARCH_V8R): Reindent.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMPLE_2.
+	(aarch64_insn_class): Add ldstgv_indexed.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
+	and AARCH64_OPND_ADDR_SIMM13.
+	(aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (aarch64_opnd): Add
+	AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10 as new enums.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
+
+2018-11-07  Roman Bolshakov <r.bolshakov@yadro.com>
+	    Saagar Jha  <saagar@saagarjha.com>
+
+	* mach-o/external.h (mach_o_nversion_min_command_external): Rename
+	reserved to sdk.
+	(mach_o_note_command_external): New.
+	(mach_o_build_version_command_external): New.
+	* mach-o/loader.h (BFD_MACH_O_LC_VERSION_MIN_TVOS): Define.
+	(BFD_MACH_O_LC_NOTE): Define.
+
+2018-11-06  Romain Margheriti  <lilrom13@gmail.com>
+
+	PR 23742
+	* mach-o/loader.h: Add BFD_MACH_O_LC_BUILD_VERSION.
+
+2018-11-06  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/arm.h (ARM_ARCH_V8_5A): Move ARM_EXT2_PREDRES and
+	ARM_EXT2_SB to ...
+	(ARM_AEXT2_V8_5A): Here.
+
+2018-10-26  John Baldwin  <jhb@FreeBSD.org>
+
+	* elf/common.h (AT_FREEBSD_HWCAP2): Define.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_SSBS): New.
+	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SSBS by default.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
+	(AARCH64_FEATURE_ID_PFR2): New.
+	(AARCH64_ARCH_V8_5): Add both by default.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
+	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
+	(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
+	(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
+	define HINT #imm values.
+	(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_RNG): New.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
+	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
+	(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
+	(aarch64_sys_regs_sr): Declare new table.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
+	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_FLAGMANIP): New.
+	(AARCH64_FEATURE_FRINTTS): New.
+	(AARCH64_ARCH_V8_5): Add both by default.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_V8_5): New.
+	(AARCH64_ARCH_V8_5): New.
+
+2018-10-08  Alan Modra  <amodra@gmail.com>
+
+	* bfdlink.h (struct bfd_link_info): Add load_phdrs field.
+
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/arm.h (ARM_EXT2_PREDRES): New.
+	(ARM_ARCH_V8_5A): Add ARM_EXT2_PREDRES by default.
+
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/arm.h (ARM_EXT2_SB): New.
+	(ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default.
+
+2018-10-05  Sudakshina Das  <sudi.das@arm.com>
+
+	* opcode/arm.h (ARM_EXT2_V8_5A): New.
+	(ARM_AEXT2_V8_5A, ARM_ARCH_V8_5A): New.
+
+2018-10-05  Richard Henderson  <rth@twiddle.net>
+
+	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_PCREL_PG21,
+	R_OR1K_GOT_PG21, R_OR1K_TLS_GD_PG21, R_OR1K_TLS_LDM_PG21,
+	R_OR1K_TLS_IE_PG21, R_OR1K_LO13, R_OR1K_GOT_LO13,
+	R_OR1K_TLS_GD_LO13, R_OR1K_TLS_LDM_LO13, R_OR1K_TLS_IE_LO13,
+	R_OR1K_SLO13, R_OR1K_PLTA26.
+
+2018-10-05  Richard Henderson  <rth@twiddle.net>
+
+	* elf/or1k.h (elf_or1k_reloc_type): Add R_OR1K_AHI16,
+	R_OR1K_GOTOFF_AHI16, R_OR1K_TLS_IE_AHI16, R_OR1K_TLS_LE_AHI16,
+	R_OR1K_SLO16, R_OR1K_GOTOFF_SLO16, R_OR1K_TLS_LE_SLO16.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* opcode/aarch64.h (aarch64_inst): Remove.
+	(enum err_type): Add ERR_VFI.
+	(aarch64_is_destructive_by_operands): New.
+	(init_insn_sequence): New.
+	(aarch64_decode_insn): Remove param name.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
+	more arguments.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* opcode/aarch64.h (enum err_type): New.
+	(aarch64_decode_insn): Use it.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* opcode/aarch64.h (struct aarch64_instr_sequence): New.
+	(aarch64_opcode_encode): Use it.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
+	* opcode/aarch64.h (struct aarch64_opcode): Add constraints,
+	extend flags field size.
+	(F_SCAN, C_SCAN_MOVPRFX, C_MAX_ELEM): New.
+
+2018-10-03  John Darrington <john@darrington.wattle.id.au>
+
+	* dis-asm.h (print_insn_s12z): New declaration.
+
+2018-10-02  Palmer Dabbelt  <palmer@sifive.com>
+
+	* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
+	(MASK_FENCE_TSO): Likewise.
+
+2018-10-01  Cupertino Miranda <cmiranda@synopsys.com>
+
+	* arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula.
+
+2018-09-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/23694
+	* include/elf/internal.h (ELF_SECTION_IN_SEGMENT_1): Don't
+	include zero size sections at start of PT_NOTE segment.
+
+2018-09-20  Nelson Chu <nelson.chu1990@gmail.com>
+
+	* elf/nds32.h: Remove the unused target features.
+	* dis-asm.h (disassemble_init_nds32): Declared.
+	* elf/nds32.h (E_NDS32_NULL): Removed.
+	(E_NDS32_HAS_DSP_INST, E_NDS32_HAS_ZOL): New.
+	* opcode/nds32.h: Ident.
+	(N32_SUB6, INSN_LW): New macros.
+	(enum n32_opcodes): Updated.
+	* elf/nds32.h: Doc fixes.
+	* elf/nds32.h: Add R_NDS32_LSI.
+	* elf/nds32.h: Add new relocations for TLS.
+
+2018-09-20  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
+
+	* elf/common.h (AT_SUN_HWCAP): Rename to ...
+	(AT_SUN_CAP_HW1): ... this.  Retain old name for backward
+	compatibility.
+	(AT_SUN_EMULATOR, AT_SUN_BRANDNAME, AT_SUN_BRAND_AUX1)
+	(AT_SUN_BRAND_AUX2, AT_SUN_BRAND_AUX3, AT_SUN_CAP_HW2): Define.
+
+2018-09-05  Simon Marchi  <simon.marchi@ericsson.com>
+
+	* diagnostics.h (DIAGNOSTIC_IGNORE_FORMAT_NONLITERAL): New macro.
+
+2018-08-31  Alan Modra  <amodra@gmail.com>
+
+	* elf/ppc64.h (R_PPC64_REL16_HIGH, R_PPC64_REL16_HIGHA),
+	(R_PPC64_REL16_HIGHER, R_PPC64_REL16_HIGHERA),
+	(R_PPC64_REL16_HIGHEST, R_PPC64_REL16_HIGHESTA): Define.
+	(R_PPC64_LO_DS_OPT, R_PPC64_16DX_HA): Bump value.
+
+2018-08-30  Kito Cheng  <kito@andestech.com>
+
+	* opcode/riscv.h (MAX_SUBSET_NUM): New.
+	(riscv_opcode): Add xlen_requirement field and change type of
+	subset.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS264E.
+	* opcode/mips.h (CPU_XXX): New CPU_GS264E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+	* opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
+	E_MIPS_MACH_GS464.
+	(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
+	* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
+	(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
+	* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
+	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT2.
+	* opcode/mips.h (ASE_LOONGSON_EXT2): New macro.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	 * elf/mips.h (AFL_ASE_LOONGSON_EXT): New macro.
+	 (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_EXT.
+	 * opcode/mips.h (ASE_LOONGSON_EXT): New macro.
+
+2018-08-29  Chenghua Xu  <paul.hua.gm@gmail.com>
+
+	* elf/mips.h (AFL_ASE_LOONGSON_CAM): New macro.
+	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_CAM.
+	* opcode/mips.h (ASE_LOONGSON_CAM): New macro.
+
+2018-08-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* elf/common.h (GNU_PROPERTY_X86_ISA_1_USED): Renamed to ...
+	(GNU_PROPERTY_X86_COMPAT_ISA_1_USED): This.
+	(GNU_PROPERTY_X86_ISA_1_NEEDED): Renamed to ...
+	(GNU_PROPERTY_X86_COMPAT_ISA_1_NEEDED): This.
+	(GNU_PROPERTY_X86_ISA_1_XXX): Renamed to ...
+	(GNU_PROPERTY_X86_COMPAT_ISA_1_XXX): This.
+	(GNU_PROPERTY_X86_UINT32_AND_LO): New.
+	(GNU_PROPERTY_X86_UINT32_AND_HI): Likewise.
+	(GNU_PROPERTY_X86_UINT32_OR_LO): Likewise.
+	(GNU_PROPERTY_X86_UINT32_OR_HI): Likewise.
+	(GNU_PROPERTY_X86_UINT32_OR_AND_LO): Likewise.
+	(GNU_PROPERTY_X86_UINT32_OR_AND_HI): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_CMOV): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_SSE): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_SSE2): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_SSE3): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_SSSE3): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_SSE4_1): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_SSE4_2): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX2): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_FMA): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512F): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512CD): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512ER): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512PF): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512VL): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512BW): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_BITALG): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_IFMA): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2): Likewise.
+	(GNU_PROPERTY_X86_ISA_1_AVX512_VNNI): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_X86): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_X87): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_MMX): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_XMM): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_YMM): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_ZMM): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_FXSR): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_XSAVE): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_2_XSAVEC): Likewise.
+	(GNU_PROPERTY_X86_FEATURE_1_AND): Updated to
+	(GNU_PROPERTY_X86_UINT32_AND_LO + 0).
+	(GNU_PROPERTY_X86_ISA_1_NEEDED): Defined to
+	(GNU_PROPERTY_X86_UINT32_OR_LO + 0).
+	(GNU_PROPERTY_X86_FEATURE_2_NEEDED): New.  Defined to
+	(GNU_PROPERTY_X86_UINT32_OR_LO + 1).
+	(GNU_PROPERTY_X86_ISA_1_USED): Defined to
+	(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 0).
+	(GNU_PROPERTY_X86_FEATURE_2_USED): New.  Defined to
+	(GNU_PROPERTY_X86_UINT32_OR_AND_LO + 1).
+
+2018-08-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* elf/common.h (GNU_PROPERTY_X86_UINT32_VALID): New.
+
+2018-08-21  John Darrington  <john@darrington.wattle.id.au>
+
+	* elf/s12z.h: Rename R_S12Z_UKNWN_3 to R_S12Z_EXT18.
+
+2018-08-21  Alan Modra  <amodra@gmail.com>
+
+	* opcode/ppc.h (struct powerpc_operand): Correct "insert" comment.
+	Mention use of "extract" function to provide default value.
+	(PPC_OPERAND_OPTIONAL_VALUE): Delete.
+	(ppc_optional_operand_value): Rewrite to use extract function.
+
+2018-08-18  John Darrington  <john@darrington.wattle.id.au>
+
+	* opcode/s12z.h: New file.
+
+2018-08-09  Richard Earnshaw  <rearnsha@arm.com>
+
+	* elf/arm.h: Updated comments for e_flags definitions.
+
+2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* elf/arc.h (Tag_ARC_ATR_version): New tag.
+
+2018-08-06  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* opcode/arc.h (ARC_OPCODE_ARCV1): Define.
+
+2018-08-01  Richard Earnshaw  <rearnsha@arm.com>
+
+	Copy over from GCC
+	2018-07-26  Martin Liska  <mliska@suse.cz>
+
+	PR lto/86548
+	* libiberty.h (make_temp_file_with_prefix): New function.
+
+2018-07-30  Jim Wilson  <jimw@sifive.com>
+
+	* opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR)
+	(INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE)
+	(INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New.
+
+2018-07-30  Andrew Jenner  <andrew@codesourcery.com>
+
+	* elf/common.h (EM_CSKY, EM_CSKY_OLD): Define.
+	* elf/csky.h: New file.
+
+2018-07-27  Chenghua Xu  <paul.hua.gm@gmail.com>
+	    Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* elf/mips.h (AFL_ASE_MASK): Correct typo.
+
+2018-07-26  Alex Chadwick  <Alex.Chadwick@cl.cam.ac.uk>
+
+	* opcode/ppc.h (PPC_OPCODE_750): Adjust comment.
+
+2018-07-26  Alan Modra  <amodra@gmail.com>
+
+	* elf/ppc64.h: Specify byte offset to local entry for values
+	of two to six in STO_PPC64_LOCAL_MASK.  Clarify r2 return
+	value for such functions when entering via global entry point.
+	Specify meaning of a value of one in STO_PPC64_LOCAL_MASK.
+
+2018-07-24  Alan Modra  <amodra@gmail.com>
+
+	PR 23430
+	* elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo.
+
+2018-07-20  Chenghua Xu  <paul.hua.gm@gmail.com>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* elf/mips.h (AFL_ASE_MMI): New macro.
+	(AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI.
+	* opcode/mips.h (ASE_LOONGSON_MMI): New macro.
+
+2018-07-17  Maciej W. Rozycki  <macro@mips.com>
+
+	* bfdlink.h (bfd_link_hash_entry): Add `rel_from_abs' member.
+
+2018-07-06  Alan Modra  <amodra@gmail.com>
+
+	* diagnostics.h: Comment on macro usage.
+
+2018-07-05  Simon Marchi  <simon.marchi@polymtl.ca>
+
+	* diagnostics.h (DIAGNOSTIC_IGNORE_DEPRECATED_DECLARATIONS):
+	Define for clang.
+
+2018-07-02  Maciej W. Rozycki  <macro@mips.com>
+
+	PR tdep/8282
+	* dis-asm.h (disasm_option_arg_t): New typedef.
+	(disasm_options_and_args_t): Likewise.
+	(disasm_options_t): Add `arg' member, document members.
+	(disassembler_options_mips): New prototype.
+	(disassembler_options_arm, disassembler_options_powerpc)
+	(disassembler_options_s390): Update prototypes.
+
+2018-06-29  Tamar Christina  <tamar.christina@arm.com>
+
+	PR binutils/23192
+	*opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.
+
+2018-06-26  Alan Modra  <amodra@gmail.com>
+
+	* elf/internal.h (ELF_SECTION_IN_SEGMENT): Revert last change.
+
+2018-06-24  Nick Clifton  <nickc@redhat.com>
+
+	2.31 branch created.
+
+2018-06-21  Alan Hayward  <alan.hayward@arm.com>
+
+	* elf/internal.h (ELF_SECTION_IN_SEGMENT): Don’t check addresses
+	for non SHT_NOBITS.
+
+2018-06-19  Simon Marchi  <simon.marchi@ericsson.com>
+
+	Sync with GCC
+
+	2018-05-24  Tom Rix  <trix@juniper.net>
+
+	* dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New.
+
+	2017-11-20  Kito Cheng  <kito.cheng@gmail.com>
+
+	* longlong.h [__riscv] (__umulsidi3): Define.
+	[__riscv] (umul_ppmm): Likewise.
+	[__riscv] (__muluw3): Likewise.
+
+2018-06-14  Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+
+	* elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros.
+	(AFL_ASE_MASK): Update to include AFL_ASE_GINV.
+	* opcode/mips.h: Document "+\" operand format.
+	(ASE_GINV): New macro.
+
+2018-06-13  Scott Egerton  <scott.egerton@imgtec.com>
+	    Faraz Shahbazker  <Faraz.Shahbazker@mips.com>
+
+	* elf/mips.h (AFL_ASE_CRC): New macro.
+	(AFL_ASE_MASK): Update to include AFL_ASE_CRC.
+	* opcode/mips.h (ASE_CRC): New macro.
+	* opcode/mips.h (ASE_CRC64): Likewise.
+
+2018-06-04  Max Filippov  <jcmvbkbc@gmail.com>
+
+	* elf/xtensa.h (xtensa_read_table_entries)
+	(xtensa_compute_fill_extra_space): New declarations.
+
+2018-06-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* diagnostics.h (DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): Always
+	define for GCC.
+
+2018-06-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* diagnostics.h (DIAGNOSTIC_STRINGIFY_1): New.
+	(DIAGNOSTIC_STRINGIFY): Likewise.
+	(DIAGNOSTIC_IGNORE): Replace STRINGIFY with DIAGNOSTIC_STRINGIFY.
+	(DIAGNOSTIC_IGNORE_SELF_MOVE): Define empty if not defined.
+	(DIAGNOSTIC_IGNORE_DEPRECATED_REGISTER): Likewise.
+	(DIAGNOSTIC_IGNORE_UNUSED_FUNCTION): Likewise.
+	(DIAGNOSTIC_IGNORE_SWITCH_DIFFERENT_ENUM_TYPES): Likewise.
+	(DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION): New.
+
+2018-06-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* diagnostics.h: Moved from ../gdb/common/diagnostics.h.
+
+2018-05-28  Bernd Edlinger  <bernd.edlinger@hotmail.de>
+
+	* splay-tree.h (splay_tree_compare_strings,
+	splay_tree_delete_pointers): Declare new utility functions.
+
+2018-05-21  Peter Bergner  <bergner@vnet.ibm.com.com>
+
+	* opcode/ppc.h (PPC_OPERAND_FAKE): Delete macro.
+
+2018-05-18  Kito Cheng  <kito.cheng@gmail.com>
+
+	* elf/riscv.h (EF_RISCV_RVE): New define.
+
+2018-05-18  John Darrington  <john@darrington.wattle.id.au>
+
+	* elf/s12z.h: New header.
+
+2018-05-15  Tamar Christina  <tamar.christina@arm.com>
+
+	PR binutils/21446
+	* opcode/aarch64.h (F_SYS_READ, F_SYS_WRITE): New.
+
+2018-05-15  Tamar Christina  <tamar.christina@arm.com>
+
+	PR binutils/21446
+	* opcode/aarch64.h (aarch64_operand_error): Add non_fatal.
+	(aarch64_print_operand): Support notes.
+
+2018-05-15  Tamar Christina  <tamar.christina@arm.com>
+
+	PR binutils/21446
+	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
+	(aarch64_decode_insn): Accept error struct.
+
+2018-05-15  Francois H. Theron  <francois.theron@netronome.com>
+
+	* opcode/nfp.h: Use uint64_t instead of bfd_vma.
+
+2018-05-10  John Darrington  <john@darrington.wattle.id.au>
+
+	* elf/common.h (EM_S12Z): New macro.
+
+2018-05-09  Sebastian Rasmussen  <sebras@gmail.com>
+
+	* mach-o/unwind.h (MACH_O_UNWIND_X86_64_RBP_FRAME_REGISTERS):
+	Rename from MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS.
+	(MACH_O_UNWIND_X86_EBP_FRAME_REGISTERS): Rename from
+	MACH_O_UNWIND_X86_EBP_FRAME_REGSITERS.
+
+2018-05-08  Jim Wilson  <jimw@sifive.com>
+
+	* opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New.
+	(MATCH_C_SRAI64, MASK_C_SRAI64): New.
+	(MATCH_C_SLLI64, MASK_C_SLLI64): New.
+
+2018-05-07  Peter Bergner  <bergner@vnet.ibm.com.com>
+
+	* opcode/ppc.h (powerpc_num_opcodes): Change type to unsigned.
+	(vle_num_opcodes): Likewise.
+	(spe2_num_opcodes): Likewise.
+
+2018-05-04  Alan Modra  <amodra@gmail.com>
+
+	* ansidecl.h: Import from gcc.
+	* coff/internal.h (struct internal_scnhdr): Add ATTRIBUTE_NONSTRING
+	to s_name.
+	(struct internal_syment): Add ATTRIBUTE_NONSTRING to _n_name.
+
+2018-04-30  Francois H. Theron <francois.theron@netronome.com>
+
+	* dis-asm.h: Added print_nfp_disassembler_options prototype.
+	* elf/common.h: Added EM_NFP, officially assigned. See Google Group
+	Generic System V Application Binary Interface.
+	* elf/nfp.h: New, for NFP support.
+	* opcode/nfp.h: New, for NFP support.
+
+2018-04-25  Christophe Lyon  <christophe.lyon@st.com>
+	Mickaël Guêné  <mickael.guene@st.com>
+
+	* elf/arm.h: Add R_ARM_TLS_GD32_FDPIC, R_ARM_TLS_LDM32_FDPIC,
+	R_ARM_TLS_IE32_FDPIC.
+
+2018-04-25  Christophe Lyon  <christophe.lyon@st.com>
+	Mickaël Guêné  <mickael.guene@st.com>
+
+	* elf/arm.h (R_ARM_GOTFUNCDESC, R_ARM_GOTOFFFUNCDESC)
+	(R_ARM_FUNCDESC)
+	(R_ARM_FUNCDESC_VALUE): Define new relocations.
+
+2018-04-25  Christophe Lyon  <christophe.lyon@st.com>
+	Mickaël Guêné  <mickael.guene@st.com>
+
+	* elf/arm.h (EF_ARM_FDPIC): New.
+
+2018-04-18  Alan Modra  <amodra@gmail.com>
+
+	* coff/mipspe.h: Delete.
+
+2018-04-18  Alan Modra  <amodra@gmail.com>
+
+	* aout/dynix3.h: Delete.
+
+2018-04-17 Andrew Sadek  <andrew.sadek.se@gmail.com>
+
+	Microblaze Target: PIC data text relative
+
+	* bfdlink.h (Add flag): Add new flag @ 'bfd_link_info' struct.
+	* elf/microblaze.h (Add 3 new relocations):
+	R_MICROBLAZE_TEXTPCREL_64, R_MICROBLAZE_TEXTREL_64
+	and R_MICROBLAZE_TEXTREL_32_LO for relax function.
+
+2018-04-17  Alan Modra  <amodra@gmail.com>
+
+	* elf/i370.h: Revert removal.
+	* elf/i860.h: Likewise.
+	* elf/i960.h: Likewise.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* coff/sparc.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* aout/host.h: Remove m68k-aout and m68k-coff support.
+	* aout/hp300hpux.h: Delete.
+	* coff/apollo.h: Delete.
+	* coff/aux-coff.h: Delete.
+	* coff/m68k.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* dis-asm.h: Remove sh5 and sh64 support.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* coff/internal.h: Remove w65 support.
+	* coff/w65.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* coff/we32k.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* coff/internal.h: Remove m88k support.
+	* coff/m88k.h: Delete.
+	* opcode/m88k.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* elf/i370.h: Delete.
+	* opcode/i370.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* coff/h8500.h: Delete.
+	* coff/internal.h: Remove h8500 support.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* coff/h8300.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* ieee.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* aout/host.h: Remove newsos3 support.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* nlm/ChangeLog-9315: Delete.
+	* nlm/alpha-ext.h: Delete.
+	* nlm/common.h: Delete.
+	* nlm/external.h: Delete.
+	* nlm/i386-ext.h: Delete.
+	* nlm/internal.h: Delete.
+	* nlm/ppc-ext.h: Delete.
+	* nlm/sparc32-ext.h: Delete.
+
+2018-04-16  Alan Modra  <amodra@gmail.com>
+
+	* opcode/tahoe.h: Delete.
+
+2018-04-11  Alan Modra  <amodra@gmail.com>
+
+	* aout/adobe.h: Delete.
+	* aout/reloc.h: Delete.
+	* coff/i860.h: Delete.
+	* coff/i960.h: Delete.
+	* elf/i860.h: Delete.
+	* elf/i960.h: Delete.
+	* opcode/i860.h: Delete.
+	* opcode/i960.h: Delete.
+	* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
+	* aout/ar.h (ARMAGB): Remove.
+	* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
+	union internal_auxent): Remove i960 support.
+
+2018-04-09  Alan Modra  <amodra@gmail.com>
+
+	* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
+	* elf/ppc64.h (R_PPC64_PLTSEQ, R_PPC64_PLTCALL): Define.
+
+2018-03-28  Renlin Li  <renlin.li@arm.com>
+
+	PR ld/22970
+	* elf/aarch64.h: Add relocation number for
+	R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12,
+	R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC,
+	R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12,
+	R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC,
+	R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12,
+	R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC,
+	R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12,
+	R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC.
+
+2018-03-28  Nick Clifton  <nickc@redhat.com>
+
+	PR 22988
+	* opcode/aarch64.h (enum aarch64_opnd): Add
+	AARCH64_OPND_SVE_ADDR_R.
+
+2018-03-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* elf/common.h (DF_1_KMOD): New.
+	(DF_1_WEAKFILTER): Likewise.
+	(DF_1_NOCOMMON): Likewise.
+
+2018-03-14  Kito Cheng  <kito.cheng@gmail.com>
+
+	* opcode/riscv.h (OP_MASK_FUNCT3): New.
+	(OP_SH_FUNCT3): Likewise.
+	(OP_MASK_FUNCT7): Likewise.
+	(OP_SH_FUNCT7): Likewise.
+	(OP_MASK_OP2): Likewise.
+	(OP_SH_OP2): Likewise.
+	(OP_MASK_CFUNCT4): Likewise.
+	(OP_SH_CFUNCT4): Likewise.
+	(OP_MASK_CFUNCT3): Likewise.
+	(OP_SH_CFUNCT3): Likewise.
+	(riscv_insn_types): Likewise.
+
+2018-03-13  Nick Clifton  <nickc@redhat.com>
+
+	PR 22113
+	* coff/pe.h (struct pex64_unwind_info): Add a rawUnwindCodesEnd
+	field.
+
+2018-03-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* opcode/i386 (OLDGCC_COMPAT): Removed.
+
+2018-02-27  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* opcode/arm.h (ARM_FEATURE_COPY): Remove macro definition.
+
+2018-02-20  Maciej W. Rozycki  <macro@mips.com>
+
+	* opcode/mips.h: Remove `M' operand code.
+
+2018-02-12  Zebediah Figura  <z.figura12@gmail.com>
+
+	* coff/msdos.h: New header.
+	* coff/pe.h: Move common defines to msdos.h.
+	* coff/powerpc.h: Likewise.
+
+2018-01-13  Nick Clifton  <nickc@redhat.com>
+
+	2.30 branch created.
+
+2018-01-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/22393
+	* bfdlink.h (bfd_link_info): Add separate_code.
+
+2018-01-04  Jim Wilson  <jimw@sifive.com>
+
+	* opcode/riscv-opc.h (CSR_SBADADDR): Rename to CSR_STVAL.  Rename
+	DECLARE_CSR entry.  Add alias to map sbadaddr to CSR_STVAL.
+	(CSR_MBADADDR): Rename to CSR_MTVAL.  Rename DECLARE_CSR entry.
+	Add alias to map mbadaddr to CSR_MTVAL.
+
+2018-01-03  Alan Modra  <amodra@gmail.com>
+
+	Update year range in copyright notice of all files.
+
+For older changes see ChangeLog-2017
+
+Copyright (C) 2018 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End: