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author | Orjan Friberg <orjanf@axis.com> | 2005-02-01 14:24:55 +0000 |
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committer | Orjan Friberg <orjanf@axis.com> | 2005-02-01 14:24:55 +0000 |
commit | ff2c3e5dc8fc0900046c0dbaf29ef1f75aa9d564 (patch) | |
tree | ef0f7fbd989152cc6eb1d5b8fd60a393781ed341 /gdb | |
parent | bb700d785171ef80b094bf9e491b38d4a0eedd54 (diff) | |
download | binutils-ff2c3e5dc8fc0900046c0dbaf29ef1f75aa9d564.zip binutils-ff2c3e5dc8fc0900046c0dbaf29ef1f75aa9d564.tar.gz binutils-ff2c3e5dc8fc0900046c0dbaf29ef1f75aa9d564.tar.bz2 |
2005-02-01 Orjan Friberg <orjanf@axis.com>
* regformats/reg-cris.dat: New file with register definitions for CRIS.
* regformats/reg-crisv32.dat: Ditto for CRISv32.
Diffstat (limited to 'gdb')
-rw-r--r-- | gdb/ChangeLog | 5 | ||||
-rw-r--r-- | gdb/regformats/reg-cris.dat | 35 | ||||
-rw-r--r-- | gdb/regformats/reg-crisv32.dat | 54 |
3 files changed, 94 insertions, 0 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index acd5de0..d2d49112 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2005-02-01 Orjan Friberg <orjanf@axis.com> + + * regformats/reg-cris.dat: New file with register definitions for CRIS. + * regformats/reg-crisv32.dat: Ditto for CRISv32. + 2005-01-31 Andrew Cagney <cagney@gnu.org> * configure: Regenerate to track ../gettext.m4. diff --git a/gdb/regformats/reg-cris.dat b/gdb/regformats/reg-cris.dat new file mode 100644 index 0000000..c63be53 --- /dev/null +++ b/gdb/regformats/reg-cris.dat @@ -0,0 +1,35 @@ +name:cris +expedite:r8,sp,pc +32:r0 +32:r1 +32:r2 +32:r3 +32:r4 +32:r5 +32:r6 +32:r7 +32:r8 +32:r9 +32:r10 +32:r11 +32:r12 +32:r13 +32:sp +32:pc + +8:p0 +8:vr +0:p2 +0:p3 +16:p4 +16:ccr +0:p6 +32:mof +32:p8 +32:ibr +32:irp +32:srp +32:bar +32:dccr +32:brp +32:usp diff --git a/gdb/regformats/reg-crisv32.dat b/gdb/regformats/reg-crisv32.dat new file mode 100644 index 0000000..565ac70 --- /dev/null +++ b/gdb/regformats/reg-crisv32.dat @@ -0,0 +1,54 @@ +name:cris +expedite:r8,sp,pc +32:r0 +32:r1 +32:r2 +32:r3 +32:r4 +32:r5 +32:r6 +32:r7 +32:r8 +32:r9 +32:r10 +32:r11 +32:r12 +32:r13 +32:sp +32:acr + +8:bz +8:vr +32:pid +8:srs +16:wz +32:exs +32:eda +32:mof +32:dz +32:ebp +32:erp +32:srp +32:nrp +32:ccs +32:usp +32:spc + +32:pc + +32:s0 +32:s1 +32:s2 +32:s3 +32:s4 +32:s5 +32:s6 +32:s7 +32:s8 +32:s9 +32:s10 +32:s11 +32:s12 +32:s13 +32:s14 +32:s15 |