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authorAndrew Burgess <andrew.burgess@embecosm.com>2021-02-15 16:07:48 +0000
committerAndrew Burgess <andrew.burgess@embecosm.com>2021-03-05 17:21:41 +0000
commitd782d24b3297d0eebdc3c823bd41993e5d670c88 (patch)
tree0c294480083a2cfa40cc2770432beef83bf0150a /gdb
parentdb6092f3aec43ea4d10efc5ff74274f04cdc0ad6 (diff)
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gdb/riscv: make riscv target description names global
A later commit will need the names of the RISC-V target description features in files other than riscv-tdep.c. This commit just makes the names global strings that can be accessed from other riscv-*.c files. There should be no user visible changes after this commit. gdb/ChangeLog: * riscv-tdep.c (riscv_feature_name_csr): Define. (riscv_feature_name_cpu): Define. (riscv_feature_name_fpu): Define. (riscv_feature_name_virtual): Define. (riscv_xreg_feature): Use riscv_feature_name_cpu. (riscv_freg_feature): Use riscv_feature_name_fpu. (riscv_virtual_feature): Use riscv_feature_name_virtual. (riscv_csr_feature): Use riscv_feature_name_csr. * riscv-tdep.h (riscv_feature_name_csr): Declare.
Diffstat (limited to 'gdb')
-rw-r--r--gdb/ChangeLog12
-rw-r--r--gdb/riscv-tdep.c14
-rw-r--r--gdb/riscv-tdep.h3
3 files changed, 25 insertions, 4 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 1a1076a..74d10f6 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,4 +1,16 @@
2021-03-05 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * riscv-tdep.c (riscv_feature_name_csr): Define.
+ (riscv_feature_name_cpu): Define.
+ (riscv_feature_name_fpu): Define.
+ (riscv_feature_name_virtual): Define.
+ (riscv_xreg_feature): Use riscv_feature_name_cpu.
+ (riscv_freg_feature): Use riscv_feature_name_fpu.
+ (riscv_virtual_feature): Use riscv_feature_name_virtual.
+ (riscv_csr_feature): Use riscv_feature_name_csr.
+ * riscv-tdep.h (riscv_feature_name_csr): Declare.
+
+2021-03-05 Andrew Burgess <andrew.burgess@embecosm.com>
Craig Blackmore <craig.blackmore@embecosm.com>
* Makefile.in (ALL_TARGET_OBS): Add riscv-none-tdep.o.
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index da86ed1..ca3efaf 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -94,6 +94,12 @@ static unsigned int riscv_debug_unwinder = 0;
static unsigned int riscv_debug_gdbarch = 0;
+/* The names of the RISC-V target description features. */
+const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
+static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
+static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
+static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
+
/* Cached information about a frame. */
struct riscv_unwind_cache
@@ -257,7 +263,7 @@ riscv_register_feature::register_info::check
struct riscv_xreg_feature : public riscv_register_feature
{
riscv_xreg_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.cpu")
+ : riscv_register_feature (riscv_feature_name_cpu)
{
m_registers = {
{ RISCV_ZERO_REGNUM + 0, { "zero", "x0" } },
@@ -354,7 +360,7 @@ static const struct riscv_xreg_feature riscv_xreg_feature;
struct riscv_freg_feature : public riscv_register_feature
{
riscv_freg_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.fpu")
+ : riscv_register_feature (riscv_feature_name_fpu)
{
m_registers = {
{ RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } },
@@ -482,7 +488,7 @@ static const struct riscv_freg_feature riscv_freg_feature;
struct riscv_virtual_feature : public riscv_register_feature
{
riscv_virtual_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.virtual")
+ : riscv_register_feature (riscv_feature_name_virtual)
{
m_registers = {
{ RISCV_PRIV_REGNUM, { "priv" } }
@@ -518,7 +524,7 @@ static const struct riscv_virtual_feature riscv_virtual_feature;
struct riscv_csr_feature : public riscv_register_feature
{
riscv_csr_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.csr")
+ : riscv_register_feature (riscv_feature_name_csr)
{
m_registers = {
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index d1f1cf1..154097d 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -160,4 +160,7 @@ extern void riscv_supply_regset (const struct regset *regset,
struct regcache *regcache, int regnum,
const void *regs, size_t len);
+/* The names of the RISC-V target description features. */
+extern const char *riscv_feature_name_csr;
+
#endif /* RISCV_TDEP_H */