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| author | Jim Wilson <jimw@sifive.com> | 2019-01-03 11:12:17 -0800 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-01-03 11:13:24 -0800 |
| commit | 592d8c0a5d193d3aad03437942a54a667477acea (patch) | |
| tree | 19055230c1af8da0c23a16fdd1b3ea1f20c9371d /gdb | |
| parent | ef1ad42b8b5f2c43d74582d2e629841c39962c18 (diff) | |
| download | binutils-592d8c0a5d193d3aad03437942a54a667477acea.zip binutils-592d8c0a5d193d3aad03437942a54a667477acea.tar.gz binutils-592d8c0a5d193d3aad03437942a54a667477acea.tar.bz2 | |
RISC-V: Fix wrong use of s0 register name.
s0 is listed as both an int register name and an FP register name. The FP reg
name is wrong. This looks like a simple editting error, and has an easy fix.
Tested with riscv64-linux build and check, with no regressions.
gdb/
* riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8.
Diffstat (limited to 'gdb')
| -rw-r--r-- | gdb/ChangeLog | 4 | ||||
| -rw-r--r-- | gdb/riscv-tdep.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 92ba43d..7d5fc45 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,7 @@ +2019-01-03 Jim Wilson <jimw@sifive.com> + + * riscv-tdep.c (riscv_freg_feature): Drop s0 name from f8. + 2019-01-02 Tom Tromey <tom@tromey.com> * xml-tdesc.c (xml_cache): Hold a target_desc_up. diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 33c1c44..7a21efc 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -185,7 +185,7 @@ static const struct riscv_register_feature riscv_freg_feature = { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true }, { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true }, { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true }, - { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true }, + { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true }, { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true }, { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true }, { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true }, |