diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:25 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-11-30 17:50:25 +0000 |
| commit | 3de8c82a4af7c9a0b5901d154cd74b59490aa16e (patch) | |
| tree | 672c25035d4945a84eac519ce6a20b4975d7a263 /gdb | |
| parent | ed96bdcba59ec5bba01de1b1db398f338f9200b1 (diff) | |
| download | binutils-3de8c82a4af7c9a0b5901d154cd74b59490aa16e.zip binutils-3de8c82a4af7c9a0b5901d154cd74b59490aa16e.tar.gz binutils-3de8c82a4af7c9a0b5901d154cd74b59490aa16e.tar.bz2 | |
aarch64: Make LOR registers conditional on +lor
We have a +lor feature flag for the Limited Ordering Regions
extension, but the associated registers didn't use it.
opcodes/
* aarch64-opc.c (SR_LOR): New macro.
(aarch64_sys_regs): Use it for lorc_el1, lorea_el1, lorn_el1 and
lorsa_el1.
gas/
* testsuite/gas/aarch64/sysreg-7.s: Enable +lor.
* testsuite/gas/aarch64/illegal-sysreg-7.s: Test for LOR registers
without +lor.
* testsuite/gas/aarch64/illegal-sysreg-7.d: Update accordingly.
* testsuite/gas/aarch64/illegal-sysreg-7.l: Likewise.
Diffstat (limited to 'gdb')
0 files changed, 0 insertions, 0 deletions