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| author | Nathan Sidwell <nathan@acm.org> | 2023-04-11 17:47:31 -0400 |
|---|---|---|
| committer | Nathan Sidwell <nathan@acm.org> | 2023-04-11 17:47:31 -0400 |
| commit | 0481d5dce311303025c6e55cd584db1870ad2492 (patch) | |
| tree | 168cf3ab18f78c5705d105ea0dc7ac0d09072491 /gdb/testsuite/gdb.rocm/fork-exec-non-gpu-to-gpu-execer.cpp | |
| parent | d8ca1d2fc58765e14463db4906eefd8296663834 (diff) | |
| download | binutils-0481d5dce311303025c6e55cd584db1870ad2492.zip binutils-0481d5dce311303025c6e55cd584db1870ad2492.tar.gz binutils-0481d5dce311303025c6e55cd584db1870ad2492.tar.bz2 | |
bfd: optimize bfd_elf_hash
The bfd_elf_hash loop is taken straight from the sysV document, but it
is poorly optimized. This refactoring removes about 5 x86 insns from
the 15 insn loop.
1) The if (..) is meaningless -- we're xoring with that value, and of
course xor 0 is a nop. On x86 (at least) we actually compute the xor'd
value and then cmov. Removing the if test removes the cmov.
2) The 'h ^ g' to clear the top 4 bits is not needed, as those 4 bits
will be shifted out in the next iteration. All we need to do is sink
a mask of those 4 bits out of the loop.
3) anding with 0xf0 after shifting by 24 bits can allow betterin
encoding on RISC ISAs than masking with '0xf0 << 24' before shifting.
RISC ISAs often require materializing larger constants.
bfd/
* elf.c (bfd_elf_hash): Refactor to optimize loop.
(bfd_elf_gnu_hash): Refactor to use 32-bit type.
Diffstat (limited to 'gdb/testsuite/gdb.rocm/fork-exec-non-gpu-to-gpu-execer.cpp')
0 files changed, 0 insertions, 0 deletions