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authorAndrew Burgess <andrew.burgess@embecosm.com>2018-10-16 22:40:09 +0100
committerAndrew Burgess <andrew.burgess@embecosm.com>2018-10-23 10:32:34 +0100
commit0dbfcfffe9abbc5198bce95eb8c66b6bc9b364be (patch)
tree389fd6bdc0b2f58914bfbdf59b28ea798ae5be33 /gdb/python
parentba37fe2e8b13194a1ef216f4224d7521e748e1cf (diff)
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gdb/riscv: Fix register access for register aliases
Some confusion over how the register names and aliases are setup in riscv means that we currently can't access registers through their architectural name. This commit fixes this issue, and moves some of the csr register handling out of the alias handling code and deals with it separately. This has the benefit that we can now directly access some arrays rather than having to iterate over them. A new test is added to ensure that register aliases now work correctly. gdb/ChangeLog: * riscv-tdep.c (riscv_gdb_reg_names): Update comment, and all register names. (struct register_alias): Rename to... (struct riscv_register_alias): ...this, and update comment. (riscv_register_aliases): Update type, and alias names. Remove CSR names from this list. (riscv_register_name): Use riscv_gdb_reg_names for int and float register names. Add an extra assertion. (riscv_is_regnum_a_named_csr): New function. (riscv_register_reggroup_p): Use riscv_is_regnum_a_named_csr. gdb/testsuite/ChangeLog: * gdb.arch/riscv-reg-aliases.c: New file. * gdb.arch/riscv-reg-aliases.exp: New file.
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