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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2026-01-05 17:50:55 +0000 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2026-01-05 17:50:55 +0000 |
| commit | 43d523e207616e970814ee9c5ca18e0b4eb89be6 (patch) | |
| tree | 812af9a2d12b76d5cc138b58b3c9c60920543cd3 /gdb/python/python.h | |
| parent | 859d7ccd9f9b1c995df4e74b227f141405cae842 (diff) | |
| download | binutils-43d523e207616e970814ee9c5ca18e0b4eb89be6.zip binutils-43d523e207616e970814ee9c5ca18e0b4eb89be6.tar.gz binutils-43d523e207616e970814ee9c5ca18e0b4eb89be6.tar.bz2 | |
aarch64: Add support for POE2 PLBI instruction
This patch adds support for PLB invalidate operation (PLBI) instruction
and the corresponding system registers as operand (<plbi_op>).
Syntax: PLBI <plbi_op>{, <Xt>}
This instruction is an alias to "SYS #<op1>, C10, <Cm>, #<op2>{, <Xt>}"
and PLBI being the preferred disassembly.
The following list of system registers are supported in this patch for the
PLBI instructions enabled by "+poe2" flag and also the "nxs" variants of
these system registers are enabled by "+poe2+xs" flag.
* alle1
* alle1is
* alle1os
* alle2
* alle2is
* alle2os
* alle3
* alle3is
* alle3os
* aside1
* aside1is
* aside1os
* permae1
* permae1is
* permae1os
* perme1
* perme1is
* perme1os
* perme2
* perme2is
* perme2os
* perme3
* perme3is
* perme3os
* vmalle1
* vmalle1is
* vmalle1os
Diffstat (limited to 'gdb/python/python.h')
0 files changed, 0 insertions, 0 deletions