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| author | Jiawei <jiawei@iscas.ac.cn> | 2024-08-20 10:10:21 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-08-27 10:25:49 +0800 |
| commit | ca2590d7804b4ea563eec6f1127ed17a00c30315 (patch) | |
| tree | 850d78027e02d5d5e9cf5eb4fda22c6f9ade5cfd /gdb/python/py-disasm.c | |
| parent | 47649afc965a611478f3dc42c43772ca8f182df4 (diff) | |
| download | binutils-ca2590d7804b4ea563eec6f1127ed17a00c30315.zip binutils-ca2590d7804b4ea563eec6f1127ed17a00c30315.tar.gz binutils-ca2590d7804b4ea563eec6f1127ed17a00c30315.tar.bz2 | |
RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'.
All disassemble instructions use the sreg format.
Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
gas/ChangeLog:
PR 32036
* NEWS: Updated.
* config/tc-riscv.c (validate_riscv_insn): New operators.
(riscv_ip): Ditto.
* testsuite/gas/riscv/zcmp-mv.d: New test.
* testsuite/gas/riscv/zcmp-mv.s: New test.
include/ChangeLog:
PR 32036
* opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode.
(MASK_CM_MVA01S): New mask.
(MATCH_CM_MVSA01): New opcode.
(MASK_CM_MVSA01): New mask.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (OP_MASK_SREG1): New mask.
(OP_SH_SREG1): New operand code.
(OP_MASK_SREG2): New mask.
(OP_SH_SREG2): New operand code.
(X_A0): New reg number.
(X_A1): Ditto.
(X_S7): Ditto.
(RISCV_SREG_0_7): New macro function.
opcodes/ChangeLog:
PR 32036
* riscv-dis.c (riscv_zcmp_get_sregno): New function.
(print_insn_args): New operators.
* riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
Diffstat (limited to 'gdb/python/py-disasm.c')
0 files changed, 0 insertions, 0 deletions