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authorLi Xu <xuli1@eswincomputing.com>2022-12-14 07:32:40 +0000
committerNelson Chu <nelson@rivosinc.com>2022-12-14 17:23:12 +0800
commit207cc92d92c863298c530498e2dbf71a2b5fd8ae (patch)
treecb511015d63057430220e610218660331642843f /gdb/glibc-tdep.c
parenteb99386180bb187f3ef3a59b222f16c8dfe3b81e (diff)
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RISC-V: Add string length check for operands in AS
The current AS accepts invalid operands due to miss of operands length check. For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma), but it's still accepted by assembler. In detail, the condition check "strncmp (array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64", "e6", 2)" in the case above. So the generated encoding is same as that of (vsetvli a0, a1, e64, mf8, tu, ma). This patch fixes issue above by prompting an error in such case and also adds a new testcase. gas/ChangeLog: * config/tc-riscv.c (arg_lookup): Add string length check for operands. * testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew. * testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise.
Diffstat (limited to 'gdb/glibc-tdep.c')
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