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author | Sandra Loosemore <sloosemore@baylibre.com> | 2024-11-26 19:13:07 +0000 |
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committer | Sandra Loosemore <sloosemore@baylibre.com> | 2024-11-26 19:13:07 +0000 |
commit | 7b55df8eff6f750c1226f87db57f2e6546638b12 (patch) | |
tree | fd41fef7b194fa8dc4b6a5caa5a522efda3e9bfb /gdb/doc | |
parent | dfc65d0579444ec020b309637654cbe17cb9dc60 (diff) | |
download | binutils-7b55df8eff6f750c1226f87db57f2e6546638b12.zip binutils-7b55df8eff6f750c1226f87db57f2e6546638b12.tar.gz binutils-7b55df8eff6f750c1226f87db57f2e6546638b12.tar.bz2 |
nios2: Remove all GDB support for Nios II targets.
Intel has EOL'ed the Nios II architecture, and it's time to remove support
from all toolchain components before it gets any more bit-rotten from
lack of maintenance or regular testing.
Diffstat (limited to 'gdb/doc')
-rw-r--r-- | gdb/doc/gdb.texinfo | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 7c6059d..85ac3d9 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -26426,7 +26426,6 @@ all uses of @value{GDBN} with the architecture, both native and cross. * MIPS:: * HPPA:: HP PA architecture * PowerPC:: -* Nios II:: * Sparc64:: * S12Z:: * AMD GPU:: @acronym{AMD GPU} architectures @@ -27015,25 +27014,6 @@ by joining the even/odd register pairs @code{f0} and @code{f1} for @code{$dl0}, For POWER7 processors, @value{GDBN} provides a set of pseudo-registers, the 64-bit wide Extended Floating Point Registers (@samp{f32} through @samp{f63}). -@node Nios II -@subsection Nios II -@cindex Nios II architecture - -When @value{GDBN} is debugging the Nios II architecture, -it provides the following special commands: - -@table @code - -@item set debug nios2 -@kindex set debug nios2 -This command turns on and off debugging messages for the Nios II -target code in @value{GDBN}. - -@item show debug nios2 -@kindex show debug nios2 -Show the current setting of Nios II debugging messages. -@end table - @node Sparc64 @subsection Sparc64 @cindex Sparc64 support @@ -49008,7 +48988,6 @@ registers using the capitalization used in the description. * MIPS Features:: * M68K Features:: * NDS32 Features:: -* Nios II Features:: * OpenRISC 1000 Features:: * PowerPC Features:: * RISC-V Features:: @@ -49841,16 +49820,6 @@ overlapping 64-bit double-precision registers. Listing 32-bit single-precision registers explicitly is deprecated, and the support to it could be totally removed some day. -@node Nios II Features -@subsection Nios II Features -@cindex target descriptions, Nios II features - -The @samp{org.gnu.gdb.nios2.cpu} feature is required for Nios II -targets. It should contain the 32 core registers (@samp{zero}, -@samp{at}, @samp{r2} through @samp{r23}, @samp{et} through @samp{ra}), -@samp{pc}, and the 16 control registers (@samp{status} through -@samp{mpuacc}). - @node OpenRISC 1000 Features @subsection Openrisc 1000 Features @cindex target descriptions, OpenRISC 1000 features |