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authorJin Ma <jinma@linux.alibaba.com>2023-11-18 15:05:31 +0800
committerNelson Chu <nelson@rivosinc.com>2023-11-23 09:31:43 +0800
commit763c4daa35a9f98533d91309917ae70d51893064 (patch)
treeb1ea311ea777e7d1871960497247d926f749d075 /gdb/ctfread.c
parent0bd0e6522a8763828d8ff6e5886ebd7fd14141e0 (diff)
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RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds provides load/store segment instructions for T-Head VECTOR vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector extension, but belongs to the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add test. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
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