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authorChristoph Müllner <christoph.muellner@vrull.eu>2022-11-13 16:59:20 +0100
committerNelson Chu <nelson@rivosinc.com>2022-11-17 16:43:49 +0800
commit4a3bc79bf4c0e89c876c930a1e95a02213277460 (patch)
tree4a82c5fbaf454ec2fcf147c1134d67b2f38d5879 /gdb/breakpoint.c
parent7a4ce4a1bcff9710b7dede9797e6d5eb2364c06e (diff)
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RISC-V: Add T-Head Fmv vendor extension
This patch adds the XTheadFmv extension, which allows to access the upper 32 bits of a double-precision floating-point register in RV32. The XTheadFmv extension is documented in the RISC-V toolchain contentions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
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